参数资料
型号: ISL88706IP844Z
厂商: Intersil
文件页数: 8/15页
文件大小: 0K
描述: IC SUPERVISOR MPU 4.38V 8-PDIP
标准包装: 50
类型: 简单复位/加电复位
监视电压数目: 1
输出: 开路漏极或开路集电极
复位: 低有效
复位超时: 最小为 140 ms
电压 - 阀值: 4.38V
工作温度: -40°C ~ 85°C
安装类型: 通孔
封装/外壳: 8-DIP(0.300",7.62mm)
供应商设备封装: 8-PDIP
包装: 管件
ISL88705, ISL88706, ISL88707, ISL88708, ISL88716, ISL88813
.
C POR
ISL88707, ISL88708
Watchdog Timer
The Watchdog Timer circuit checks microprocessor activity
by monitoring the WDI input pin. The microprocessor must
periodically toggle the WDI pin within t WDT (typically ~1.6s),
otherwise the WDO pin pulls low (see Figure 5). The WDO
then signals reset periodically (typically ~1.9s) for ~220ms
until the WDI is again toggled. Internally, the 1.6s timer is
cleared by either a reset or by toggling the WDI input, which
can detect pulses longer than 50ns.
Whenever there is a low-voltage V DD condition, WDO goes
14
12
10
8
6
4
2
0
NORMALIZED t POR vs C POR (pF)
OPEN = 200ms
low. Unlike the reset outputs, however, WDO does not have
a minimum reset pulse width (t POR ). WDO goes high as
soon as V DD rises above its voltage trip point (see Figure 5).
With WDI open or connected to a tristated high impedance
input, the Watchdog Timer is disabled and only pulls low
when V DD < V TH1.
0
10
20
30
40
50
60
70
80
90
100
C POR (pF)
FIGURE 3. ADJUSTING t POR WITH A CAPACITOR
Manual Reset
The manual-reset input (MR) allows the user to trigger a
reset by using a push-button switch. The MR input is an
active low debounced input. By connecting a push-button
directly from MR to ground, the designer adds manual
system reset capability (see Figure 4). Reset is asserted if
the MR pin is pulled low to less than 100mV for the minimum
MR pulse width or longer while the push-button is closed.
After MR is released, the reset outputs remain asserted for
t POR (200ms) and then released.
20k
MR
PB
ISL8870x
FIGURE 4. CONNECTING A MANUAL RESET PUSH-BUTTON
8
FN8092.5
January 12, 2009
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