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参数资料
| 型号： | ISL88708IB831Z-TK |
| 厂商： | Intersil |
| 文件页数： | 4/15页 |
| 文件大小： | 0K |
| 描述： | IC SUPERVISOR MPU 3.09V 8-SOIC |
| 产品培训模块： | Voltage Supervisors Solutions for Industrial Control Applications |
| 标准包装： | 1 |
| 类型： | 简单复位/加电复位 |
| 监视电压数目： | 1 |
| 输出： | 开路漏极，推挽式 |
| 复位： | 高有效/低有效 |
| 复位超时： | 最小为 140 ms |
| 电压 - 阀值： | 3.09V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 8-SOIC（0.154"，3.90mm 宽） |
| 供应商设备封装： | 8-SOIC |
| 包装： | 标准包装 |
| 产品目录页面： | 1235 (CN2011-ZH PDF) |
| 其它名称： | ISL88708IB831Z-TKDKR |
ISL88705, ISL88706, ISL88707, ISL88708, ISL88716, ISL88813
Pin Descriptions
ISL88705, ISL88716, ISL88707,
ISL88706
ISL88813
ISL88708 NAME
DESCRIPTION
1
1
1
MR
Manual Reset Input. A reset signal is generated when this input is pulled low. The MR input is an
active low debounced input to which a user can connect a push-button to add manual reset capability
or drive with a signal. The MR pin has an internal 20k Ω pull-up.
2
2
2
V DD
Power Supply Terminal. The voltage at this pin is compared against an internal factory-programmed
voltage trip point, V TH1 . A reset is first asserted when the device is initially powered up to ensure that
the power supply has stabilized. Thereafter, reset is again asserted whenever V DD falls below V TH1 .
The device is designed with hysteresis to help prevent chattering due to noise and is immune to brief
power-supply transients. The voltage threshold V TH1 is specified in the part number suffix.
3
4
3
4
3
4
GND
PFI
Ground Connection
Power-Fail Input This is an auxiliary monitored voltage input with a 1.25V threshold that causes PFO
state to follow the PFI input state.
5
5
5
PFO
Power-Fail Output. This output goes high if the voltage on PFI is greater than 1.25V, otherwise PFO
stays low.
6
C POR Adjustable POR Time-out Delay Input. Connecting an external capacitor from C POR to ground
allows the user to increase the Power-On Reset time-out (t POR ) from the nominal 200ms.
6
6
WDI
Watchdog Input. The Watchdog Input takes an input from a microprocessor and ensures that it
periodically toggles the WDI pin, otherwise the internal nominal 1.6s watchdog timer runs out, then
reset is asserted and WDO is pulled low. The internal Watchdog Timer is cleared whenever the WDI
sees a rising or falling edge or the device is manually reset. Floating WDI or connecting WDI to a
high-impedance three-state buffer disables the watchdog feature.
7
7
RST
Active-Low Reset Output. The RST output is an active low output with an internal PMOS pull-up
that is pulled low to GND when reset is asserted. Reset is asserted whenever:
1. The device is first powered up
2. V DD falls below its minimum voltage sense level or
3. MR is asserted.
The reset output continues to be asserted for typically 200ms after V DD rises above the reset
threshold or MR input goes from low to high. A watchdog time-out will not trigger a reset unless WDO
is connected to MR.
7
8
RST
Active-High Reset Output. The RST pin functions identically to its complementary RST output but
is an active high push-pull output. RST is set high to V DD when reset is asserted. See the RST in “Pin
8
8
WDO
Watchdog Output . This output is pulled low when the nominal 1.6s internal Watchdog Timer expires
and periodically resets until the watchdog is cleared. WDO also goes low during low V DD conditions.
Whenever V DD is below the reset threshold, WDO stays low. However, unlike RESET, WDO does
not have a minimum pulse width. As soon as V DD rises above the reset threshold, WDO goes high
with no delay.
4
FN8092.5
January 12, 2009
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