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参数资料
| 型号： | ISL88813IB846Z-TK |
| 厂商： | Intersil |
| 文件页数： | 6/15页 |
| 文件大小： | 0K |
| 描述： | IC SUPERVISOR MPU 4.64V 8-SOIC |
| 产品培训模块： | Voltage Supervisors |
| 标准包装： | 1 |
| 类型： | 简单复位/加电复位 |
| 监视电压数目： | 1 |
| 输出： | 推挽式，图腾柱 |
| 复位： | 高有效 |
| 复位超时： | 最小为 140 ms |
| 电压 - 阀值： | 4.64V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 8-SOIC（0.154"，3.90mm 宽） |
| 供应商设备封装： | 8-SOIC |
| 包装： | 剪切带 (CT) |
| 其它名称： | ISL88813IB846Z-TKCT |
ISL88705, ISL88706, ISL88707, ISL88708, ISL88716, ISL88813
Electrical Specifications
Over the recommended operating conditions unless otherwise specified. Parameters with MIN and/or MAX
limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization
and are not production tested. (Continued)
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
MANUAL RESET
V MRL
V MRH
t MR
R PU
MR Input Voltage Low
MR Input Voltage High
MR Minimum Pulse Width
Internal MR Pull-Up Resistor
V DD - 0.6
550
20
0.8
V
V
ns
k Ω
WATCHDOG TIMER (Note 2)
t WDT
Watchdog Time-out Period
1.0
1.6
2.0
s
t WDPS
V IL
V IH
WDI Minimum Pulse Width
Watchdog Input Voltage Low
Watchdog Input Voltage High
100
0.7 x V DD
0.3 x V DD
ns
V
V
V WDOL
WDO Output Voltage Low
V DD ≥ 3.3V, Sinking 2.5mA
V DD < 3.3V, Sinking 1.5mA
0.05
0.05
0.40
0.40
V
V
V WDOH
I WDT
WDO Output Voltage High
Watchdog Input Current
V DD ≥ 3.3V, Sourcing 2.5mA
V DD < 3.3V, Sourcing 1.5mA
V DD - 0.6
V DD - 0.6
V DD - 0.4
V DD - 0.4
1
V
V
μA
POWER-FAIL DETECTION
V THPFI
PFI Input Threshold Voltage
MR = Open
1.20
1.25
1.30
V
PFIV THHYST Hysteresis Voltage
20
mV
V PFOL
PFO Output Voltage Low
V DD ≥ 3.3V, Sinking 2.5mA
V DD < 3.3V, Sinking 1.5mA
0.05
0.05
0.40
0.40
V
V
V PFOH
PFO Output Voltage High
V DD ≥ 3.3V, Sourcing 2.5mA
V DD < 3.3V, Sourcing 1.5mA
V DD - 0.6
V DD - 0.6
V DD - 0.4
V DD - 0.4
V
V
NOTE:
2. Applies to ISL88705, ISL88706, ISL88716, and ISL88813.
Principles of Operation
The ISL88705, ISL88706, ISL88707, ISL88708, ISL88716,
ISL88813 devices provide those functions needed for
monitoring critical voltages such as power-supply and battery
functions in microprocessor systems. Features of these
supervisors include Power-On Reset control, Supply Voltage
Supervision, Power-Fail Detection and Manual Reset
Assertion. The integration of all these features along with high
reset threshold accuracy and low power consumption make
these devices ideal for portable or battery-powered equipment.
6
Power-On Reset (POR)
Applying power to the device activates a POR circuit which
asserts reset (i.e. RST goes high while RST goes low). These
signals provide several benefits:
? It prevents the system microprocessor from starting to
operate with insufficient voltage.
? It prevents the processor from operating prior to stabilization
of the oscillator.
? It ensures that the monitored device is held out of operation
until internal registers are properly loaded.
? It allows time for an FPGA to download its configuration prior
to initialization of the circuit.
The reset signals remain active until V DD rises above the
minimum voltage sense level for time period t POR . This
ensures that the supply voltage has stabilized to sufficient
operating levels.
FN8092.5
January 12, 2009
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