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| 型号： | ISL89163FRTCZ |
| 厂商： | Intersil |
| 文件页数： | 10/15页 |
| 文件大小： | 0K |
| 描述： | MOSFET DRIVER 2CH 6A 8TDFN |
| 标准包装： | 100 |
| 配置： | 低端 |
| 输入类型： | 非反相 |
| 延迟时间： | 25ns |
| 电流 - 峰： | 6A |
| 配置数： | 2 |
| 输出数： | 2 |
| 电源电压： | 7.5 V ~ 16 V |
| 工作温度： | -40°C ~ 125°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 8-WFDFN 裸露焊盘 |
| 供应商设备封装： | 8-TDFN（3x3） |
| 包装： | 管件 |
ISL89163, ISL89164, ISL89165
Functional Description
Overview
The ISL89163, ISL89164, ISL89165 MOSFET drivers incorporate
several features optimized for Synchronous Rectifier (SR) driver
D
R del
ENx
INx
c del
OUTx
applications including precision input logic thresholds, enable
inputs, undervoltage lock-out, and high amplitude output drive
currents.
The precision input thresholds facilitate the use of an external RC
network to delay the rising or falling propagation of the driver
output. This is a useful feature for adjusting when the SRs turn on
relative to the primary side FETs. In a similar manner, these
drivers can also be used to control the turn-on/off timing of the
primary side FETs.
The Enable inputs (ENA, ENB) are used to emulate diode
operation of the SRs by disabling the driver output when it is
necessary to prevent negative currents in the output filter
inductors. An example is turning off the SRs when the power
supply output is turned off. This prevents the output capacitor
FIGURE 18. DELAY USING RCD NETWORK
In Figure 18, R del and C del delay the rising edge of the input
signal. For the falling edge of the input signal, the diode shorts
out the resistor resulting in a minimal falling edge delay.
The 37% and 63% thresholds of options A and B were chosen to
simplify the calculations for the desired time delays. When using
an RC circuit to generate a time delay, the delay is simply
T (secs) = R (ohms) x C (farads). Please note that this equation
only applies if the input logic voltage is matched to the 3.3V or 5V
threshold options. If the logic high amplitude is not equal to 3.3V
or 5V, then the equations in Equation 1 can be used for more
precise delay calculations.
from being discharged through the output inductor. If this is
allowed to happen, the voltage across the output capacitor will
ring negative possibly damaging the capacitor (if it is polarized)
and probably damaging the load. Another example is preventing
circulating currents between paralleled power supplies during no
or light load conditions. During light load conditions (especially
VH = 10V
Vthres = 63% × 5 V
VL = .3V
Rdel = 100 Ω
High level of the logic signal into the RC
Positive going threshold for 5V logic (B option)
Low level of the logic signal into the RC
Timing values
tdel = ? Rdel C del × ln ?
when active load sharing is not active), energy will be transferred
from the paralleled power supply that has a higher voltage to the
paralleled power supply with the lower voltage. Consequently, the
energy that is absorbed by the low voltage output is then
C del = 1nF
? VL ? Vthres
? V H ? VL
?
+ 1 ?
?
transferred to the primary side causing the bus voltage to
increase until the primary side is damaged by excessive voltage.
tdel = 34.788 ns
nominal delay time for this example
(EQ. 1)
The start-up sequence for input threshold options A, B, and C is
designed to prevent unexpected glitches when V DD is being
turned on or turned off. When V DD < ~1V, an internal 10k ?
resistor connected between the output and ground, help to keep
the gate voltage close to ground. When ~1V < V DD < UV, both
outputs are driven low while ignoring the logic inputs. This low
state has the same current sinking capacity as during normal
operation. This insures that the driven FETs are held off even if
there is a switching voltage on the drains that can inject charge
into the gates via the Miller capacitance. When V DD > UVLO, and
after a 400μs delay, the outputs now respond to the logic inputs.
See Figure 9 for complete details.
For the negative transition of V DD through the UV lockout voltage,
the outputs of input threshold options A or B are active low when
V DD < ~3.2V DC regardless of the input logic states. Similarly, the
C option outputs are active low when V DD < ~6.5V DC .
Application Information
Precision Thresholds for Time Delays
Three input logic voltage levels are supported by the ISL89163,
ISL89164, ISL89165. Option A is used for 3.3V logic, Option B is
used for 5.0V logic, and Option C is used for higher voltage logic
when it is desired to have voltage thresholds that are
proportional to V DD . The A and B options have nominal
thresholds that are 37% and 63% of 3.3V and 5.0V respectively
and the C option is 20% and 80% of V DD .
10
In this example, the high logic voltage is 10V, the positive
threshold is 63% of 5V and the low level logic is 0.3V. Note the
rising edge propagation delay of the driver must be added to this
value.
The minimum recommended value of C is 100pF. The parasitic
capacitance of the PCB and any attached scope probes will
introduce significant delay errors if smaller values are used.
Larger values of C will further minimize errors.
Acceptable values of R are primarily effected by the source
resistance of the logic inputs. Generally, 100 ? resistors or larger are
usable.
Paralleling Outputs to Double the Peak Drive
Currents
The typical propagation matching of the ISL8963 and ISL89164
is less than 1ns. The matching is so precise that carefully
matched and calibrated scopes probes and scope channels must
be used to make this measurement. Because of this excellent
performance, these driver outputs can be safely paralleled to
double the current drive capacity. It is important that the INA and
INB inputs be connected together on the PCB with the shortest
possible trace. This is also required of OUTA and OUTB. Note that
the ISL89165 cannot be paralleled because of the
complementary logic.
FN7707.3
March 7, 2012
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相关代理商/技术参数 |
参数描述 |
|---|---|
| ISL89163FRTCZ-T | 功能描述:MOSFET DRIVER 2CH 6A 8TDFN RoHS:是 类别:集成电路 (IC) >> PMIC - MOSFET，电桥驱动器 - 外部开关 系列:- 标准包装:6,000 系列:* |
| ISL89164FBEAZ | 功能描述:MOSFET DRIVER 2CH 3.3V 6A 8SOIC RoHS:是 类别:集成电路 (IC) >> PMIC - MOSFET，电桥驱动器 - 外部开关 系列:- 标准包装:50 系列:- 配置:高端 输入类型:非反相 延迟时间:200ns 电流 - 峰:250mA 配置数:1 输出数:1 高端电压 - 最大（自引导启动）:600V 电源电压:12 V ~ 20 V 工作温度:-40°C ~ 125°C 安装类型:通孔 封装/外壳:8-DIP（0.300"，7.62mm） 供应商设备封装:8-DIP 包装:管件 其它名称:*IR2127 |
| ISL89164FBEAZ-T | 功能描述:MOSFET DRIVER 2CH 3.3V 6A 8SOIC RoHS:是 类别:集成电路 (IC) >> PMIC - MOSFET，电桥驱动器 - 外部开关 系列:- 标准包装:6,000 系列:* |
| ISL89164FBEBZ | 功能描述:MOSFET DRIVER 2CH 5.0V 6A 8SOIC RoHS:是 类别:集成电路 (IC) >> PMIC - MOSFET，电桥驱动器 - 外部开关 系列:- 标准包装:50 系列:- 配置:高端 输入类型:非反相 延迟时间:200ns 电流 - 峰:250mA 配置数:1 输出数:1 高端电压 - 最大（自引导启动）:600V 电源电压:12 V ~ 20 V 工作温度:-40°C ~ 125°C 安装类型:通孔 封装/外壳:8-DIP（0.300"，7.62mm） 供应商设备封装:8-DIP 包装:管件 其它名称:*IR2127 |
| ISL89164FBEBZ-T | 功能描述:MOSFET DRIVER 2CH 5.0V 6A 8SOIC RoHS:是 类别:集成电路 (IC) >> PMIC - MOSFET，电桥驱动器 - 外部开关 系列:- 标准包装:6,000 系列:* |
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