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参数资料
| 型号： | ISL89167FRTAZ-T |
| 厂商： | Intersil |
| 文件页数： | 11/14页 |
| 文件大小： | 0K |
| 描述： | IC MOSFET DRIVER 2CH 6A 8TDFN |
| 标准包装： | 6,000 |
| 配置： | 低端 |
| 输入类型： | 反相 |
| 延迟时间： | 25ns |
| 电流 - 峰： | 6A |
| 配置数： | 2 |
| 输出数： | 2 |
| 电源电压： | 4.5 V ~ 16 V |
| 工作温度： | -40°C ~ 125°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 8-WDFN 裸露焊盘 |
| 供应商设备封装： | 8-TDFN-EP（3x3） |
| 包装： | 带卷 (TR) |
ISL89166, ISL89167, ISL89168
The Typical Application Circuit is an example of how the
ISL89166, ISL89167, ISL89168, MOSFET drivers can be applied
in a zero voltage switching full bridge. Two main signals are
required: a 50% duty cycle square wave (SQR) and a PWM signal
synchronized to the edges of the SQR input. An ISL89162 is used
to drive T1 with alternating half cycles driving Q UL and Q UR . An
ISL89166 is used to drive Q LL and Q LR also with alternating half
cycles. Unlike the two high side bridge FETs, the two low-side
bridge FETs are turned on with a rising edge delay. The delay is
setup by resistors connected to RDTA and RDTB pins of the
ISL89166. The duration of the delay is chosen to turn on the
low-side FETs when the voltage on their respective drains is at the
resonant valley.
General PCB Layout Guidelines
The AC performance of the ISL89166, ISL89167, ISL89168
depends significantly on the design of the PC board. The
following layout design guidelines are recommended to achieve
optimum performance:
? Place the driver as close as possible to the driven power FET.
? Understand where the switching power currents flow. The high
amplitude di/dt currents of the driven power FET will induce
significant voltage transients on the associated traces.
? Keep power loops as short as possible by paralleling the
source and return traces.
? Use planes where practical; they are usually more effective
than parallel traces.
? Avoid paralleling high amplitude di/dt traces with low level
signal lines. High di/dt will induce currents and consequently,
that source the input signals to the ISL89166, ISL89167,
ISL89168.
? Avoid having a signal ground plane under a high amplitude
dv/dt circuit. This will inject di/dt currents into the signal
ground paths.
? Do power dissipation and voltage drop calculations of the
power traces. Many PCB/CAD programs have built in tools for
calculation of trace resistance.
? Large power components (Power FETs, Electrolytic caps, power
resistors, etc.) will have internal parasitic inductance which
cannot be eliminated.
This must be accounted for in the PCB layout and circuit
design.
? If you simulate your circuits, consider including parasitic
components especially parasitic inductance.
General EPAD Heatsinking
Considerations
The thermal pad is electrically connected to the GND supply
through the IC substrate. The epad of the ISL89166, ISL89167,
ISL89168 has two main functions: to provide a quiet GND for the
input threshold comparators and to provide heat sinking for the
IC. The EPAD must be connected to a ground plane and no
switching currents from the driven FET should pass through the
ground plane under the IC.
Figure 21 is a PCB layout example of how to use vias to remove
heat from the IC through the epad.
noise voltages in the low level signal lines.
? When practical, minimize impedances in low level signal
circuits. The noise, magnetically induced on a 10k resistor, is
10x larger than the noise on a 1k resistor.
? Be aware of magnetic fields emanating from transformers and
inductors. Gaps in these structures are especially bad for
emitting flux.
? If you must have traces close to magnetic devices, align the
traces so that they are parallel to the flux lines to minimize
EPAD GND
PLANE
COMPONENT
LAYER
EPAD GND
PLANE
BOTTOM
LAYER
coupling.
? The use of low inductance components such as chip resistors
and chip capacitors is highly recommended.
? Use decoupling capacitors to reduce the influence of parasitic
inductance in the VDD and GND leads. To be effective, these
caps must also have the shortest possible conduction paths. If
vias are used, connect several paralleled vias to reduce the
inductance of the vias.
? It may be necessary to add resistance to dampen resonating
parasitic circuits especially on OUTA and OUTB. If an external
gate resistor is unacceptable, then the layout must be
improved to minimize lead inductance.
? Keep high dv/dt nodes away from low level circuits. Guard
banding can be used to shunt away dv/dt injected currents
from sensitive circuits. This is especially true for control circuits
11
FIGURE 21. TYPICAL PCB PATTERN FOR THERMAL VIAS
For maximum heatsinking, it is recommended that a ground
plane, connected to the EPAD, be added to both sides of the PCB.
A via array, within the area of the EPAD, will conduct heat from
the EPAD to the GND plane on the bottom layer. The number of
vias and the size of the GND planes required for adequate
heatsinking is determined by the power dissipated by the
ISL89166, ISL89167, ISL89168, the air flow and the maximum
temperature of the air around the IC.
FN7720.2
February 26, 2013
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