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参数资料
| 型号： | ISL89168FBEAZ-T |
| 厂商： | Intersil |
| 文件页数： | 5/14页 |
| 文件大小： | 0K |
| 描述： | IC MOSFET DRIVER 2CH 6A 8SOIC |
| 标准包装： | 2,500 |
| 配置： | 低端 |
| 输入类型： | 反相和非反相 |
| 延迟时间： | 25ns |
| 电流 - 峰： | 6A |
| 配置数： | 2 |
| 输出数： | 2 |
| 电源电压： | 4.5 V ~ 16 V |
| 工作温度： | -40°C ~ 125°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 8-SOIC（0.154"，3.90mm Width）裸露焊盘 |
| 供应商设备封装： | 8-SOIC-EP |
| 包装： | 带卷 (TR) |
ISL89166, ISL89167, ISL89168
DC Electrical Specifications V DD = 12V, GND = 0V, No load on OUTA or OUTB, RDTA = RDTB = 0k Ω unless otherwise specified.
Boldface limits apply over the operating junction temperature range, -40°C to +125°C. (Continued)
T J = +25°C
T J = -40°C to +125°C
MIN
MAX
PARAMETERS
Input Bias Current
for INA, INB
SYMBOL
I IN
TEST CONDITIONS
GND < V IN < V DD
MIN
-
TYP
-
MAX
-
(Note 7)
-10
(Note 7)
+10
UNITS
μA
OUTPUTS
High Level Output Voltage
Low Level Output Voltage
V OHA V OHB
V OLA
V OLB
-
-
-
-
-
-
V DD - 0.1
GND
V DD
GND + 0.1
V
V
Peak Output Source Current
Peak Output Sink Current
I O
I O
V O (initial) = 0V, C LOAD = 10nF
V O (initial) = 12V, C LOAD = 10nF
-
-
-6
+6
-
-
-
-
-
-
A
A
NOTES:
7. Compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design.
8. This parameter is taken from the simulation models for the input FET. The actual capacitance on this input will be dominated by the PCB parasitic
capacitance.
9. A 400μs delay further inhibits the release of the output state when the UV positive going threshold is crossed. See Figure 9
10. The true state of a specific part number is defined by the input logic symbol.
AC Electrical Specifications V DD = 12V, GND = 0V, No Load on OUTA or OUTB, RDTA = RDTB = 0k Ω unless Otherwise
Specified. Boldface limits apply over the operating junction temperature range, -40°C to +125°C.
T J = +25°C
T J = -40°C to +125°C
TEST CONDITIONS
MIN
MAX
PARAMETERS
Output Rise Time (see Figure 4)
Output Fall Time (see Figure 4)
Output Rising Edge Propagation Delay (see Figure 3)
Output Falling Edge Propagation Delay (see Figure 3)
(Note 12)
Rising Propagation Matching (see Figure 3)
Falling Propagation Matching (see Figure 3)
Rising edge timer delay (Note 11)
Miller Plateau Sink Current
(See Test Circuit Figure 5)
SYMBOL
t R
t F
t RDLY
t FDLY
t RM
t FM
t RTDLY20
t RTDLY2
-I MP
-I MP
-I MP
/NOTES
C LOAD = 10nF,
10% to 90%
C LOAD = 10nF,
90% to 10%
RDTx = 0k Ω
RDTx = 0k Ω
RDTx = 0k Ω
RDTx = 0k Ω
RTx = 20k Ω ,
No load
RTx = 2.0k Ω , No
load
V DD = 10V,
V MILLER = 5V
V DD = 10V,
V MILLER = 3V
V DD = 10V,
V MILLER = 2V
MIN
-
-
-
-
-
-
-
-
-
-
-
TYP
20
20
25
25
<1ns
<1ns
266
42
6
4.7
3.7
MAX
-
-
-
-
-
-
-
-
-
-
-
(Note 7)
-
-
-
-
-
-
237
29
-
-
-
(Note 7)
40
40
50
50
-
-
297
58
-
-
-
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
A
A
A
5
FN7720.2
February 26, 2013
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