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参数资料
| 型号： | ISL89400ABZ |
| 厂商： | Intersil |
| 文件页数： | 5/11页 |
| 文件大小： | 0K |
| 描述： | IC DRVR H-BRDG 100V 1.25A 8SOIC |
| 产品培训模块： | Solutions for Industrial Control Applications |
| 标准包装： | 980 |
| 配置： | 半桥 |
| 输入类型： | PWM |
| 延迟时间： | 39ns |
| 电流 - 峰： | 1.25A |
| 配置数： | 1 |
| 输出数： | 2 |
| 高端电压 - 最大（自引导启动）： | 100V |
| 电源电压： | 9 V ~ 14 V |
| 工作温度： | -40°C ~ 125°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 8-SOIC（0.154"，3.90mm 宽） |
| 供应商设备封装： | 8-SOIC |
| 包装： | 管件 |
ISL89400, ISL89401
Electrical Specifications
V DD = V HB = 12V, V SS = V HS = 0V, No Load on LO or HO, unless otherwise specified. Parameters with MIN
and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by
characterization and are not production tested. (Continued)
T J = +25°C
T J = -40°C to +125°C
PARAMETERS
HB Threshold Hysteresis
SYMBOL
V HBH
TEST CONDITIONS
MIN
-
TYP
0.6
MAX
-
MIN
-
MAX
-
UNITS
V
BOOT STRAP DIODE
Low Current Forward Voltage
High Current Forward Voltage
Dynamic Resistance
V DL
V DH
R D
I VDD-HB = 100μA
I VDD-HB = 100mA
I VDD-HB = 100mA
-
-
-
0.5
0.7
0.8
0.6
0.9
1
-
-
-
0.7
1
1.5
V
V
Ω
LO GATE DRIVER
Low Level Output Voltage
High Level Output Voltage
Peak Pull-Up Current
Peak Pull-Down Current
V OLL
V OHL
I OHL
I OLL
I LO = 100mA
I LO = -100mA, V OHL = V DD - V LO
V LO = 0V
V LO = 12V
-
-
-
-
0.4
0.4
1.25
1.25
0.5
0.5
-
-
-
-
-
-
0.7
0.7
-
-
V
V
A
A
HO GATE DRIVER
Low Level Output Voltage
High Level Output Voltage
Peak Pull-up Current
Peak Pull-down Current
V OLH
V OHH
I OHH
I OLH
I HO = 100mA
I HO = -100mA, V OHH = V HB - V HO
V HO = 0V
V HO = 12V
-
-
-
-
0.4
0.4
1.25
1.25
0.5
0.5
-
-
-
-
-
-
0.7
0.7
-
-
V
V
A
A
Switching Specifications
V DD = V HB = 12V, V SS = V HS = 0V, No Load on LO or HO, Unless Otherwise Specified
TEST
T J = +25°C
T J = -40°C to +125°C
PARAMETERS
Lower Turn-off Propagation Delay (LI Falling to LO Falling)
Upper Turn-off Propagation Delay (HI Falling to HO Falling)
Lower Turn-on Propagation Delay (LI Rising to LO Rising)
Upper Turn-on Propagation Delay (HI Rising to HO Rising)
Delay Matching: Upper Turn-Off to Lower Turn-On
Delay Matching: Lower Turn-Off to Upper Turn-On
Either Output Rise/Fall Time (10% to 90%/90% to 10%)
Either Output Rise/Fall Time (3V to 9V/9V to 3V)
Minimum Input Pulse Width that Changes the Output
Bootstrap Diode Turn-On or Turn-Off Time
SYMBOL
t LPHL
t HPHL
t LPLH
t HPLH
t MON
t MOFF
t RC, t FC
t R, t F
t PW
t BS
CONDITIONS
C L = 1nF
C L = 0.1μF
MIN
-
-
-
-
1
1
-
-
-
-
TYP
34
31
39
39
8
6
16
0.8
-
10
MAX
50
50
50
50
-
-
-
1.0
-
-
MIN
-
-
-
-
-
-
-
-
-
-
MAX
60
60
60
60
16
16
-
1.2
50
-
UNITS
ns
ns
ns
ns
ns
ns
ns
μs
ns
ns
5
FN6614.2
August 11, 2009
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