参数资料
型号: ISL9103IRUWZ-T
厂商: Intersil
文件页数: 10/13页
文件大小: 0K
描述: IC REG BUCK SYNC 1.2V .5A 6UTDFN
产品培训模块: Patient Monitoring and Diagnostic Equipment Solutions
标准包装: 3,000
类型: 降压(降压)
输出类型: 固定
输出数: 1
输出电压: 1.2V
输入电压: 2.7 V ~ 6 V
PWM 型: 电流模式
频率 - 开关: 2.4MHz
电流 - 输出: 500mA
同步整流器:
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 6-UFDFN
包装: 带卷 (TR)
供应商设备封装: 6-UTDFN(1.6x1.6)
ISL9103, ISL9103A
During the 16-consecutive cycles, the inductor current could
v EAMP
v CSA
d
i L
v OUT
FIGURE 23. PWM OPERATION WAVEFORMS
The output voltage is regulated by controlling the reference
voltage to the current loop. The bandgap circuit outputs a
0.8V reference voltage to the voltage control loop. The
feedback signal comes from the FB pin. The soft-start block
only affects the operation during the start-up and will be
discussed separately in “Soft-Start” on page 11. The EAMP
is a transconductance amplifier, which converts the voltage
error signal to a current output. The voltage loop is internally
compensated by a RC network. The maximum EAMP
voltage output is precisely clamped to the bandgap voltage.
Skip Mode (PFM Mode)
Under light load condition, ISL9103, ISL9103A automatically
enters a pulse-skipping mode to minimize the switching loss
by reducing the switching frequency. Figure 24 illustrates the
skip mode operation. A zero-cross sensing circuit (as shown
in Figure 22) monitors the current flowing through SW node
for zero crossing. When it is detected to cross zero for
be negative. The counter is reset to zero when the sensed
current flowing through SW node does not cross zero during
any cycle within the 16-consecutive cycles. Once ISL9103,
ISL9103A enters the skip mode, the pulse modulation starts
being controlled by the SKIP comparator shown in Figure 22.
Each pulse cycle is still synchronized by the PWM clock. The
P-Channel MOSFET is turned on at the rising edge of clock
and turned off when its current reaches ~20% of the peak
current limit. As the average inductor current in each cycle is
higher than the average current of the load, the output
voltage rises cycle over cycle. When the output voltage is
sensed to reach 1.5% above its nominal voltage, the
P-Channel MOSFET is turned off immediately and the
inductor current is fully discharged to zero and stays at zero.
The output voltage reduces gradually due to the load current
discharging the output capacitor. When the output voltage
drops to the nominal voltage, the P-Channel MOSFET will
be turned on again, repeating the previous operations.
The regulator resumes normal PWM mode operation when
the output voltage is sensed to drop below 1.5% of its
nominal voltage value.
Enable
The enable (EN) pin allows user to enable or disable the
converter for purposes such as power-up sequencing. With
EN pin pulled to high, the converter is enabled and the
internal reference circuit wakes up first and then the soft
start-up begins. When EN pin is pulled to logic low, the
converter is disabled, both P-Channel MOSFET and
N-Channel MOSFETS are turned off, and the output
capacitor is discharged through internal discharge path.
16-consecutive cycles, the regulator enters the skip mode.
16 CYCLES
CLOCK
20% PEAK CURRENT LIMIT
I L
0
1.015*V OUT_NOMINAL
V OUT
V OUT_NOMINAL
FIGURE 24. SKIP MODE OPERATION WAVEFORMS
10
FN6828.2
November 24, 2009
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