参数资料
型号: ISL9444IRZ-T
厂商: Intersil
文件页数: 21/24页
文件大小: 0K
描述: IC REG CTRLR BUCK PWM CM 40-QFN
标准包装: 6,000
PWM 型: 电流模式
输出数: 3
频率 - 最大: 1.32MHz
电源电压: 4.5 V ~ 28 V
降压:
升压:
回扫:
反相:
倍增器:
除法器:
Cuk:
隔离:
工作温度: -40°C ~ 85°C
封装/外壳: 40-VFQFN 裸露焊盘
包装: 带卷 (TR)
ISL9444
voltages, the stray capacitor formed between these islands
and the surrounding circuitry will tend to couple switching
noise.
device turns on and off into near zero voltage. The equations
assume linear voltage-current transitions and do not model
power loss due to the reverse-recovery of the lower MOSFET’s
( I O ) ( r DS ( ON ) ) ( V OUT )
( I O ) ( V IN ) ( t SW ) ( F SW )
V IN
( I O ) ( r DS ( ON ) ) ( V IN – V OUT )
V IN
10. Route all high speed switching nodes away from the control
circuitry.
11. Create a separate small analog ground plane near the IC.
Connect the SGND pin to this plane. All small signal grounding
paths including feedback resistors, current limit setting
resistors, soft-starting capacitors and ENx pull-down resistors
should be connected to this SGND plane.
body diode.
2
2
P UPPER = ---------------------------------------------------------- + --------------------------------------------------------
2
P LOWER = ------------------------------------------------------------------------
(EQ. 14)
(EQ. 15)
12. Separate current sensing traces from PHASE node
connections.
13. Ensure the feedback connection to the output capacitor is
short and direct.
General PowerPAD Design Considerations
The following is an example of how to use vias to remove heat
from the IC.
A large gate-charge increases the switching time, t SW , which
increases the upper MOSFETs’ switching losses. Ensure that both
MOSFETs are within their maximum junction temperature at high
ambient temperature by calculating the temperature rise
according to package thermal-resistance specifications.
Output Inductor Selection
The PWM converters require output inductors. The output
inductor is selected to meet the output voltage ripple
requirements. The inductor value determines the converter’s
ripple current and the ripple voltage is a function of the ripple
current and the output capacitor(s) ESR. The ripple voltage
expression is given in the capacitor selection section and the
ripple current is approximated by Equation 16:
( V IN – V OUT ) ( V OUT )
( F SW ) ( L ) ( V IN )
Δ I L = ---------------------------------------------------
(EQ. 16)
Output Capacitor Selection
The output capacitors for each output have unique requirements.
FIGURE 29. PCB VIA PATTERN
It is recommended to fill the thermal pad area with vias. A typical
via array fills the thermal pad footprint such that their centers are
3x the radius apart from each other. Keep the vias small but not
so small that their inside diameter prevents solder wicking
through during reflow.
Connect all vias to the ground plane. It is important the vias have
a low thermal resistance for efficient heat transfer. It is
important to have a complete connection of the plated-through
hole to each plane.
Component Selection Guideline
MOSFET Considerations
The logic level MOSFETs are chosen for optimum efficiency given
the potentially wide input voltage range and output power
requirements. Two N-Channel MOSFETs are used in each of the
synchronous-rectified buck converters for the 3 PWM outputs.
These MOSFETs should be selected based upon r DS(ON) , gate
supply requirements, and thermal management considerations.
In general, the output capacitors should be selected to meet the
dynamic regulation requirements including ripple voltage and
load transients. Selection of output capacitors is also dependent
on the output inductor, so some inductor analysis is required to
select the output capacitors.
One of the parameters limiting the converter’s response to a load
transient is the time required for the inductor current to slew to
its new level. The ISL9444 will provide either 0% or maximum
duty cycle in response to a load transient.
The response time is the time interval required to slew the
inductor current from an initial current value to the load current
level. During this interval, the difference between the inductor
current and the transient current level must be supplied by the
output capacitor(s). Minimizing the response time can minimize
the output capacitance required. Also, if the load transient rise
time is slower than the inductor response time, as in a hard
drive or CD drive, it reduces the requirement on the output
capacitor.
The maximum capacitor value required to provide the full, rising
step, transient load current during the response time of the
inductor is:
( L O ) ( I TRAN )
2 ( V IN – V O ) ( DV OUT )
Power dissipation includes two loss components: conduction
loss and switching loss. These losses are distributed between
the upper and lower MOSFETs according to duty cycle (see
Equations 14 and 15). The conduction losses are the main
2
C OUT = -----------------------------------------------------
(EQ. 17)
component of power dissipation for the lower MOSFETs. Only the
upper MOSFET has significant switching losses, since the lower
21
Where C OUT is the output capacitor(s) required, L O is the output
inductor, I TRAN is the transient load current step, V IN is the input
FN7665.3
May 29, 2012
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