参数资料
| 型号： | ISL9491ERZ-T |
| 厂商： | Intersil |
| 文件页数： | 12/13页 |
| 文件大小： | 0K |
| 描述： | IC REG SGL LNB CONTROL 16QFN |
| 标准包装： | 6,000 |
| 应用： | 转换器，卫星信号接收机顶盒设计 |
| 输入电压： | 8 V ~ 14 V |
| 输出数： | 1 |
| 输出电压： | 13.3 V ~ 20 V |
| 工作温度： | -20°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 16-VQFN 裸露焊盘 |
| 供应商设备封装： | 16-QFN-EP（4x4） |
| 包装： | 带卷 (TR) |
ISL9491, ISL9491A, ISL9491A
due to hard short on the output. The current limiting
described so far is called “Dynamic Current” limiting
which limits current to approximately 750mA for 50ms
and turns off the output for 900ms. R ILIM is used to
program the current level at which the ISL9491 enters
External Output Voltage Selection
The pin VSET0 and VSET1 are provided for switching
between typical output voltages, as indicated in Table 1.
TABLE 1.
into this protection mode. On the other hand, the
ISL9491 can also be programmed in “Static Current
Limit” mode which defeats the 50ms/900ms(on/off)
pulse by delivering constant 750mA load current to the
system by using a 0 Ω R ILIMIT resistor. In this mode the
chip will deliver this current to the load for as long as the
die junction temperature is less than 130 o C. Figure 16
shows the static current limit by shorting the output to
GND. It also shows that initially the chip delivers 750mA
but the junction starts heating up since approximately
EN
0
1
1
1
1
VSET1
X
0
0
1
1
VSET0
X
0
1
0
1
VLNB
ISL9491
Disabled
13.3V
18.3V
14.3V
20.0V
VLNB
ISL9491A
Disabled
11.0V
15.0V
12.0V
16.0V
10W (13.3V*0.75A) is being dissipated internally. The
thermal shutdown circuitry takes over and shuts the
output LDO stage-off after approximately 50ms and the
load current drops to zero as seen in Figure 17. The chip
restarts as soon as the junction temperature drops below
the thermal shutdown level but quickly shuts off in 15ms
as seen in Figure 18.
The CS pin provides peak current protection for the Boost
FET on a pulse-by-pulse basis. Once the voltage on the
FET source sense resistor crosses 0.45V typical, the
Boost FET drive is set to low. The sense resistor can be
sized to limit the peak current through the FET. It is
highly recommended to have a boost current limit of
200% when sizing the sense resistor to accommodate
high current transients in the boost circuit.
Thermal Protection
This IC is protected against overheating. When the
junction temperature exceeds +130°C (typical), the
step-up converter and the linear regulator are shut-off.
When the junction is cooled down to +110°C (typical),
normal operation is resumed.
Output Over/Undervoltage Fault and EXTM
The recommended start-up sequence is Vcc going high
followed by ENABLE while EXTM is pulled low. This will
start the output voltage to ramp up with a dv/dt which is
based on the TCAP value. Once ENABLE is pulled high,
allow a 50ms delay before applying 22kHz/44kHz, 50%
square pulse on EXTM pin to generate the DISEQ tone on
the output. At this point, FAULT should also be high,
indicating that output voltage is in regulation. FAULT is
designed to stay high when the output voltage is
commanded to transition between the values listed in
Table 1, and also when passing the DiSEQ tone on the
output. FAULT will immediately pull low if there is a short
on the output or if the voltage falls outside the ± 10%
window indicating that the voltage is out of regulation.
FAULT signal is armed after the first initial power-up
when output voltage is in steady-state. If tone is applied
to the EXTM pin before the chip is ENABLED, it causes the
FAULT to remain low even after the output voltage
reaches steady state. This issue can be resolved by
pulling the EXTM low for 2 cycles which is 90ms of
ISL9491 and 45ms for ISL9491A.
Intersil products are manufactured, assembled and tested utilizing ISO9000 quality systems as noted
in the quality certifications found at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications
at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by
Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any
infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any
patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
12
FN6531.0
October 13, 2009
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