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参数资料
| 型号： | ISL95210IRZ-T7A |
| 厂商： | Intersil |
| 文件页数： | 3/20页 |
| 文件大小： | 0K |
| 描述： | IC REG BUCK SYNC ADJ 10A 32QFN |
| 标准包装： | 1 |
| 类型： | 降压（降压） |
| 输出类型： | 可调式 |
| 输出数： | 1 |
| 输出电压： | 0.6 V ~ 2.16 V |
| 输入电压： | 2.97 V ~ 5.5 V |
| PWM 型： | R4 |
| 频率 - 开关： | 400kHz ~ 800kHz |
| 电流 - 输出： | 10A |
| 同步整流器： | 是 |
| 工作温度： | -40°C ~ 100°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 32-VFQFN 裸露焊盘 |
| 包装： | 标准包装 |
| 供应商设备封装： | 32-QFN（4x6） |
| 其它名称： | ISL95210IRZ-T7ADKR |
ISL95210
Pin Configuration
ISL95210
(32 LD QFN)
TOP VIEW
26
25
24
23
22
21
20
19
18
17
VSEL0 27
AGND 28
VOUT 29
VCC 30
MPCT 31
MSEL 32
T-PAD (PGND)
16 VIN
15 PVCC
14 PVCC
13 PGND
12 PGND
11 DNC
1
2
3
4
5
6
7
8
9
10
Functional Pin Descriptions
PIN
T-PAD
(Thermal Pad)
1
2
3
4, 5, 6,
7, 8, 9, 10
11
12, 13, 19,
20, 21, 22, 23
14, 15
16, 17, 18
24
25
26
27
NAME
PGND
FCCM
FSET
EN
PHASE
DNC
PGND
PVCC
VIN
PG_IN
PGOOD
VSEL1
VSEL0
FUNCTION
Power ground. This thermal pad provides a return path for power stage and switching currents, as well as a thermal path
for removing heat from the IC into the board. Place thermal vias in the pad to the PGND plane.
Logic input for operating mode selection. Connect this pin to VCC for CCM regulation only. Connect this pin to AGND to allow
discontinuous conduction mode for light-load efficiency. Float this pin for audio mode light-load switching.
Tri-state digital input for programming the regulator switching frequency. Pull this pin to VCC for 800kHz switching. Pull this
pin to GND for 400kHz switching. Leave this pin floating for 533kHz switching.
Logic input for enabling and disabling output voltage regulation. Pull this pin to VCC to begin regulation. Pull this pin to AGND
to disable regulation.
Power stage switching node for output voltage regulation. Connect to the output inductor. All PHASE pins must be electrically
connected together on the printed circuit board.
Do not connect. This pin must be left floating under all conditions.
Power ground. This pin provides a return path for power stage and switching currents. All PGND pins must be electrically
connected together on the printed circuit board.
Power input for the integrated MOSFET gate drivers. Connect to a 5V (±10%) supply. Both PVCC pins must be shorted on
the printed circuit board. VIN and PVCC may be tied together (see Figure 1) when operating from a nominal 5V supply.
However, PVCC requires a 5V (±10%) supply irrespective of VIN. It is connected to VCC through an integrated 10 Ω resistor
and therefore doubles as the power supply for IC bias. If VIN is below 4.5V, PVCC must receive a separate power supply
input and decoupling capacitor (1μF typical).
Power input for buck regulation stage. Bypass to PGND with one 10μF or 22μF ceramic capacitor. Connect to a 2.97V to
5.5V supply. All VIN pins must be electrically connected together on the printed circuit board.
Input voltage for the power-good CMOS output. Connect this pin to the desired PGOOD output high level.
Active CMOS output for power-good indication. High state is indicated when the output voltage is in regulation, and output
is logic low otherwise. Logic high level is set by the voltage on the PG_IN pin.
DAC logic MSB input. Used to program preset output voltages of 0.60V, 0.75V, 0.90V, 1.00V, 1.05V, 1.10V, 1.20V, 1.50V,
and 1.80V.
DAC logic LSB input. Used to program preset output voltages of 0.60V, 0.75V, 0.90V, 1.00V, 1.05V, 1.10V, 1.20V, 1.50V,
and 1.80V.
3
FN6938.4
December 15, 2011
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