参数资料
| 型号： | ISL95210IRZ |
| 厂商： | Intersil |
| 文件页数： | 16/20页 |
| 文件大小： | 0K |
| 描述： | IC REG BUCK SYNC ADJ 10A 32QFN |
| 标准包装： | 75 |
| 类型： | 降压（降压） |
| 输出类型： | 可调式 |
| 输出数： | 1 |
| 输出电压： | 0.6 V ~ 2.16 V |
| 输入电压： | 2.97 V ~ 5.5 V |
| PWM 型： | R4 |
| 频率 - 开关： | 400kHz ~ 800kHz |
| 电流 - 输出： | 10A |
| 同步整流器： | 是 |
| 工作温度： | -40°C ~ 100°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 32-VFQFN 裸露焊盘 |
| 包装： | 管件 |
| 供应商设备封装： | 32-QFN（4x6） |
ISL95210
PVCC
Selection of the Input Capacitor
The important parameters for the bulk input capacitance are the
voltage rating and the RMS current rating. For reliable operation,
select bulk capacitors with voltage and current ratings above the
maximum input voltage and capable of supplying the RMS
current required by the switching circuit. Their voltage rating
VIN = 3.3V
PVCC = 5V
CIN
10μF
1μF
VCC
VIN
PGOOD
ISL95210
PHASE
LOUT
420nH
POWER
GOOD
VOUT = 1.2V
should be at least 1.25x greater than the maximum input
voltage, while a voltage rating of 1.5x is a preferred rating.
Figure 32 is a graph of the input RMS ripple current, normalized
relative to output load current, as a function of duty cycle and is
adjusted for a converter efficiency of 80%. The ripple current
calculation is written as Equation 11:
CONTROL
SIGNALS
EN
PG_IN
FSET
VSEL1
MPCT
MSEL
VSEL0
FCCM
VOUT
VCC
AGND
PGND
T-PAD
1μF
+ COUT
220μF
( D – D ) + ? D ? ------ ?
I IN_RMS , NORMALIZED =
? 12 ?
2 x
2
(EQ. 11)
FSW = 800kHz
LOUT = MPC0740LR42C (NEC/TOKIN)
COUT = 2TPLF220M5 (SANYO)
V O
(EQ. 12)
V IN ? EFF
POWER
PVCC
GOOD
VOUT = 2.25V
VCC
VSEL1
2.49k Ω
CONTROL
AGND
PGND
T-PAD
where:
- x is a multiplier (0 to 1) corresponding to the inductor
peak-to-peak ripple amplitude expressed as a percentage of
I MAX (0% to 100%)
- D is the duty cycle that is adjusted to take into account the
efficiency of the converter, which is written as Equation 12:
D = --------------------------
In addition to the bulk capacitance, some low ESL ceramic
capacitance is recommended to decouple between the drain of
the high-side MOSFET and the source of the low-side MOSFET.
0.60
x = 0.75
0.55
0.50 x=1
0.45
0.40 x = 0.50
x = 0.25
0.35
0.30
FIGURE 33. ISL95210 TYPICAL APPLICATION WITH VIN < 5V
The second typical application variant is when the designer
wishes to program VOUT to a value not available in the DAC table.
The component selection for this configuration is described in
detail in “Output Voltage Programming” on page 11. Figure 34
shows a resistor divider programmed configuration for an output
voltage of 2.25V.
VIN = 5V VIN
PGOOD
CIN
10μF ISL95210
LOUT
PHASE
420nH
EN VOUT
PG_IN VCC 100 Ω + COUT
FSET
220μF
1μF
SIGNALS MPCT
MSEL
VSEL0
FCCM
0.25
x=0
0.20
FSW = 800kHz
LOUT = MPC0740LR42C (NEC/TOKIN)
0.15
0.10
0.05
COUT = 2TPLF220M5 (SANYO)
FIGURE 34. ISL95210 TYPICAL APPLICATION WITH VOUT = 2.5V
0
0
0.1
0.2
0.3
0.4 0.5 0.6 0.7
0.8
0.9
1.0
Layout Considerations
DUTY CYCLE
FIGURE 32. NORMALIZED RMS INPUT CURRENT
Typical Applications Circuits
There are two main variants to typical application schematic
shown in Figure 1. The first of these is when an input voltage
lower than 5V is desired. This requires the designer to provide
separate power supplies to VIN and PVCC as the ISL95210
requires a 5V bias to operate properly. Figure 33 illustrates this
configuration for a VIN of 3.3V.
16
It is important to place power components as close as possible to
the devices they decouple. Figure 35 provides an example of
proper power component placement for the ISL95210. Input
capacitors are placed directly across VIN and PGND to filter
switching currents between the PMOS and NMOS power FETs.
The output inductor is placed directly adjacent to the PHASE pins.
Its “north-south” arrangements easily allow for the output
voltage decoupling capacitor to be placed with its ground
terminal very near the input capacitors grounds and the PGND
pins of the ISL95210. This provides a low impedance return path
for the inductor ripple current. This is one possible arrangement
that will result in a good layout.
The analog ground connection (not shown) should be connected
directly to the ground plane through a via. The VCC decoupling
capacitor should be placed next to the VCC and AGND pins for
optimal noise rejection.
FN6938.4
December 15, 2011
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