参数资料
| 型号： | ISL95810UIU8Z-T |
| 厂商： | Intersil |
| 文件页数： | 2/13页 |
| 文件大小： | 0K |
| 描述： | IC POT DGTL 50K OHM 8-MSOP |
| 标准包装： | 1 |
| 系列： | XDCP™ |
| 接片： | 256 |
| 电阻（欧姆）： | 50k |
| 电路数： | 1 |
| 温度系数： | 标准值 ±45 ppm/°C |
| 存储器类型： | 非易失 |
| 接口： | I²C |
| 电源电压： | 2.7 V ~ 5.5 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 8-TSSOP，8-MSOP（0.118"，3.00mm 宽） |
| 供应商设备封装： | 8-MSOP |
| 包装： | 标准包装 |
| 产品目录页面： | 1237 (CN2011-ZH PDF) |
| 其它名称： | ISL95810UIU8Z-TDKR |
10
FN8090.2
September 19, 2006
Write Operation
A Write operation requires a START condition, followed by a
valid Identification Byte, a valid Address Byte, a Data Byte,
and a STOP condition. After each of the three bytes, the
ISL95810 responds with an ACK. At this time, if the Data
Byte is to be written only to volatile registers, then the device
enters its standby state. If the Data Byte is to be written also
to non-volatile memory, the ISL95810 begins its internal
write cycle to non-volatile memory. During the internal non-
volatile write cycle, the device ignores transitions at the SDA
and SCL pins, and the SDA output is at a high impedance
state. When the internal non-volatile write cycle is
completed, the ISL95810 enters its standby state (See
Figure 17).
The byte at address 02h determines if the Data Byte is to be
written to volatile and/or non-volatile memory (See “Memory
Data Protection
The WP pin has to be at logic HIGH to perform any Write
operation to the device. When the WP is active (LOW) the
device ignores Data Bytes of a Write Operation, does not
respond to the Data Bytes with an ACK, and instead, goes to
its standby state waiting for a new START condition.
A STOP condition also acts as a protection of non-volatile
memory. A valid Identification Byte, Address Byte, and total
number of SCL pulses act as a protection of both volatile
and non-volatile registers. During a Write sequence, the
Data Byte is loaded into an internal shift register as it is
FIGURE 16. ACKNOWLEDGE RESPONSE FROM RECEIVER
FIGURE 17. BYTE WRITE SEQUENCE
FIGURE 18. READ SEQUENCE
SDA OUTPUT FROM
TRANSMITTER
SDA OUTPUT FROM
RECEIVER
8
1
9
START
ACK
SCL FROM
MASTER
HIGH IMPEDANCE
S
T
A
R
T
S
T
O
P
IDENTIFICATION
BYTE
ADDRESS
BYTE
DATA
BYTE
A
C
K
SIGNALS FROM
THE MASTER
SIGNALS FROM
THE ISL95810
A
C
K
0
11
A
C
K
WRITE
SIGNAL AT SDA
00 0 0
0
00 0
00
SIGNALS
FROM THE
MASTER
SIGNALS FROM
THE SLAVE
SIGNAL AT SDA
S
T
A
R
T
IDENTIFICATION
BYTE WITH
R/W=0
ADDRESS
BYTE
A
C
K
A
C
K
00
0
11
S
T
O
P
A
C
K
0
1
0
11
IDENTIFICATION
BYTE WITH
R/W=1
A
C
K
S
T
A
R
T
LAST READ
DATA BYTE
FIRST READ
DATA BYTE
A
C
K
000
0
00 0
0 0
000
ISL95810
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| ISL95810WIRT8ZTR5481 | 制造商:Intersil Corporation 功能描述:ISL95810W PRE-PROGRAMMED TO LOWEST RESISTANCE SETTING, XDCP, - Tape and Reel |
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