参数资料
型号: ISL97645IRZ-TK
厂商: Intersil
文件页数: 12/16页
文件大小: 0K
描述: IC REG BOOST VON VCOM 24-QFN
标准包装: 1,000
应用: LCD 监视器,笔记本电脑显示器
电流 - 电源: 1mA
电源电压: 2.7 V ~ 5.5 V
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 24-VFQFN 裸露焊盘
供应商设备封装: 24-QFN 裸露焊盘(4x4)
包装: 带卷 (TR)
ISL97645A
Supply Monitor Circuit
The Supply Monitor circuit monitors the voltage on VDIV,
and sets open-drain output RESET low when VDIV is below
1.15V (rising) or 1.1V (falling).
There is a delay on the rising edge, controlled by a capacitor
on CD2. When VDIV exceeds 1.15V (rising), CD2 is charged
up from 0V to 1.215V by a 10μA current source. Once CD2
exceeds 1.215V, RESET will go tri-state. When VDIV falls
below 1.1V, RESET will become low with a 750 pull-down
resistance. The delay time is controlled by Equation 7:
Gate Pulse Modulator Circuit
The gate pulse modulator circuit functions as a three way
multiplexer, switching VGHM between ground, VDD1 and
VGH. Voltage selection is provided by digital inputs VDPM
(enable) and VFLK (control). High to low delay and slew
control is provided by external components on pins CE and
RE, respectively. A block diagram of the gate pulse
modulator circuit is shown in Figure 16.
When VDPM is LOW, the block is disabled and VGHM is
grounded. When the input voltage exceeds UVLO threshold,
t delay = 121.5k × CD2
(EQ. 7)
VDPM starts to drive an external capacitor with 20 μ A. Once
VDPM exceeds 1.215V, the GPM circuit is enabled, and the
output VGH_M is determined by VFLK, RESET signal and
For example, the delay time is 12.15ms if the CD2 = 100nF.
Figure 15 is the Supply Monitor Circuit timing diagram.
1.15V
VDIV
VGH voltage. If RESET signal is high, and when VFLK goes
high, VGHM is pulled to VGH by a 70 Ω switch. When VFLK
goes low, there is a delay controlled by capacitor CE,
following which VGHM is driven to VDD1, with a slew rate
controlled by resistor RE. Note that VDD1 is used only as a
reference voltage for an amplifier, thus does not have to
source or sink a significant DC current.
1.1V
Low to high transition is determined primarily by the switch
CD2
1.215V
RESET DELAY TIME IS
resistance and the external capacitive load. High to low
transition is more complex. Take the case where the block is
already enabled (VDPM is H). When VFLK is H, pin CE is
grounded. On the falling edge of VFLK, a current is passed
into pin CE, to charge an external capacitor to 1.2V. This
RESET
CONTROLLED BY CD2
CAPACITOR
creates a delay, equal to CE*4200. At this point, the output
begins to pull down from VGH to VDD1. The slew current is
equal to 300/(RE + 5000), and the dv/dt slew rate is
FIGURE 15. SUPPLY MONITOR CIRCUIT TIMING DIAGRAM
12
Isl/C LOAD .
where C LOAD is the load capacitance applied to VGHM.
When RESET signal changes to low, and VGH voltage is
above 2.5V, the VGH_M will be tied to VGH voltage until the
VGH voltage falls down to 2.5V. If the VGH voltage is lower
than 2.5V, GPM block will not work properly, and there is no
active control for VGH_M output. The following table shows
the VGH_M status based on V IN , VGH and RESET:
FN6353.1
October 21, 2010
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