参数资料
型号: ISL97646IRZ-T
厂商: Intersil
文件页数: 12/15页
文件大小: 0K
描述: IC REG BOOST LDO VON VCOM 24-QFN
标准包装: 6,000
应用: 转换器,LCD 显示器
输入电压: 2.7 V ~ 5.5 V
输出数: 2
输出电压: 8 V ~ 20 V
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 24-VFQFN 裸露焊盘
供应商设备封装: 24-QFN 裸露焊盘(4x4)
包装: 带卷 (TR)
ISL97646
The efficiency of LDO is depended on the difference
between input voltage and output voltage, as well as the
output current:
Gate Pulse Modulator Circuit
The gate pulse modulator circuit functions as a three way
multiplexer, switching VGHM between ground, VDD1 and
η ( % ) = ( V IN1 – V LDO_OUT ) × I LDO_OUT × 100%
(EQ. 7)
VGH. Voltage selection is provided by digital inputs VDPM
(enable) and VFLK (control). High to low delay and slew
The less difference between input and output voltage, the
higher efficiency it is. The minimum dropout voltage of LDO
of ISL97646 is 300mV.
The ceramic capacitors are recommended for the LDO input
and output capacitor. Larger capacitors help reduce noise
and deviation during transient load change.
control is provided by external components on pins CE and
RE, respectively. A block diagram of the gate pulse
modulator circuit is shown in Figure 16.
When VDPM is LOW, the block is disabled and VGHM is
grounded. When VDPM is HIGH, the output is determined
by VFLK. When VFLK goes high, VGHM is pulled to VGH by
a 70 Ω switch. When VFLK goes low, there is a delay
controlled by capacitor CE, following which VGHM is driven
to VDD1, with a slew rate controlled by resistor RE. Note
that VDD1 is used only as a reference voltage for an
amplifier, thus does not have to source or sink a significant
DC current.
VGH
VGH_M
EnGPM1
+
VDD1
-
x240
RE
CE
200μA
+
-
VREF
VFLK
CONTROL AND
TIMING
FIGURE 16. GATE PULSE MODULATOR CIRCUIT BLOCK DIAGRAM
12
FN6265.1
December 14, 2007
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