参数资料
型号: ISL97693IRTZ-TK
厂商: Intersil
文件页数: 22/28页
文件大小: 0K
描述: IC LED DRVR BACKLIGHT 16TQFN
标准包装: 1,000
拓扑: PWM,升压(升压)
输出数: 6
内部驱动器:
类型 - 主要: 背光
频率: 400kHz ~ 1.5MHz
电源电压: 2.5 V ~ 5.5 V
输出电压: 26V
安装类型: 表面贴装
封装/外壳: 16-WFQFN 裸露焊盘
供应商设备封装: 16-TQFN(3x3)
包装: 带卷 (TR)
工作温度: -40°C ~ 85°C
ISL97692, ISL97693, ISL97694A
pin. The AGND connection of the lower OVP components is
critical for good regulation.
4. The COMP network and the rest of the analog components
(on ISET, FPWM, FSW, etc.) should be reference to AGND.
5. The heat of the chip is mainly dissipated through the exposed
thermal pad so maximizing the copper area around is a good
idea. A solid ground is always helpful for the thermal and EMI
CH1
CH2
FIGURE 31.
PCB Layout Considerations
PCB Layout with TQFN Package
Great care is needed in designing a PC board for stable
ISL97692/3/4A operation. As shown in the typical application
diagram (Figures 3, 4 and 5 on pages 2, and 3) the separation of
PGND and AGND is essential, keeping the AGND referenced only
local to the chip. This minimizes switching noise injection to the
feedback sensing and analog areas, as well as eliminating DC
errors form high current flow in resistive PC board traces. PGND
and AGND should be on the top and bottom layers respectively in
the two layers PCB. A star ground connection should be formed
by connecting the LED ground return and AGND pins to the
thermal pad with vias (Figures 32, 33). The ground connection
should be into this ground net, on the top plane. The bottom
plane then forms a quiet analog ground area that both shields
components on the top plane, as well as providing easy access to
all sensitive components. For example, the ground side of the
ISET resistor can be dropped to the bottom plane, providing a
very low impedance path back to the AGND pin, which does not
have any circulating high currents to interfere with it. The bottom
plane can also be used as a thermal ground, so the AGND area
should be sized sufficiently large to dissipate the required power.
For multi-layer boards, the AGND plane can be the second layer.
This provides easy access to the AGND net, but allows a larger
thermal ground and main ground supply to come up through the
thermal vias from a lower plane.
Figure 34 shows the example of the PCB layout of ISL97694A.
This type of layout is particularly important for this type of
product, resulting in high current flow in the main loop’s traces.
Careful attention should be focused in the following layout
details:
1. Boost input capacitors, output capacitors, inductor and
Schottky diode should be placed together in a nice tight
layout. Keeping the grounds of the input, and output
connected with low impedance and wide metal is very
important to keep these nodes closely coupled.
2. If possible, try to maintain central ground node on the board
and use the input capacitors to avoid excessive input ripple for
high output current supplies. The filtering capacitors should
be placed close by the VIN pin.
3. For optimum load regulation and true VOUT sensing, the OVP
resistors should be connected independently to the top of the
output capacitors and away from the higher dv/dt traces. The
OVP connection then needs to be as short as possible to the
22
performance.
6. The inductor and input and output capacitors should be
mounted as tight as possible, to reduce the audible noise and
inductive ringing.
General Power PAD Design Considerations
Figures 32 and 33 show an example of how to use vias to remove
heat from the IC. We recommend you fill the thermal pad area
with vias. A typical via array would be to fill the thermal pad foot
print with vias spaced such that the centre to centre spacing is
three times the radius of the via. Keep the vias small, but not so
small that their inside diameter prevents solder wicking through
the holes during reflow.
FIGURE 32. VIA PATTERN OF ISL97692/3 TQFN
FIGURE 33. VIA PATTERN OF ISL97694A TQFN
FN7839.4
December 20, 2012
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