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| 型号： | ISL97702IRZ |
| 厂商： | Intersil |
| 文件页数： | 9/13页 |
| 文件大小： | 0K |
| 描述： | IC REG BOOST ADJ 0.13A DL 10DFN |
| 标准包装： | 100 |
| 类型： | 升压（升压） |
| 输出类型： | 可调式 |
| 输出数： | 2 |
| 输出电压： | 可调至 28V |
| 输入电压： | 2.3 V ~ 5.5 V |
| 频率 - 开关： | 1MHz |
| 电流 - 输出： | 130mA |
| 同步整流器： | 无 |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 10-VFDFN 裸露焊盘 |
| 包装： | 管件 |
| 供应商设备封装： | 10-DFN（3x3） |
| 产品目录页面： | 1249 (CN2011-ZH PDF) |
ISL97702
If NSYNC is tied to VDD the internal oscillator defines Dmax
to:
Dmax(fosc) = 1 - toff(LX)min*fosc
With external synchronization at pin NSYNC
Dmax(NSYNC) = 1 - toff(LX)min*f(NSYNC)
The duty cycle at LX can be 0% ( pulse skipping ), if the
output voltage exceeds the target voltage set with the
feedback resistors.
Internal Schottky Diode – LX, V OUT
The inductor node LX internally connects to the power FET
and to the anode of the integrated power Schottky diode.
The cathode of the diode is pin V OUT . An overvoltage
detector at V OUT continuously monitors the cathode voltage
and immediately disables the boost regulator if the voltage
FIGURE 16.
Fault Control
The input voltage at VDD, current in the VDDOUT switch,
voltage at V OUT and junction temperature Tj are
continuously monitored and can either restart the start-up
sequence or in some cases disable the ISL97702 boost
function as long as the fault is present.
TABLE 1. FAULT PROTECTION
exceeds the maximum allowable voltage.
Feedback Input Pins – FB0, FB1
Each feedback pin is either configured as feedback input pin
or as ground reference output pin for the external feedback
resistor chain. Configured as output the feedback pin is
switched to the internal reference ground via a low Ron MOS
transistor to achieve maximum accuracy of the regulated
output voltage. A current limit at FB0 and FB1 prevents
overloading in a fault condition.
FAULT
FAULT
ISL97702 FAULT
DESCRIPTION
CONDITION
REACTION
TABLE 2. PIN FEEDBACK CONFIGURATION DEPENDENT
ON SEL
Undervoltage at
V(VDD) <
Disables I/Os and waits until
VDD
Overcurrent drawn
V(VDD)off
I(VDDOUT) >
V(VDD) reaches V(VDD)on
to begin with the start-up
sequence
Disables VDDOUT switch
SEL
0
1
FB0
Feedback Input
Ground Reference Output
FB1
Ground Reference Output
Feedback Input
from VDDOUT
It(VDDOUT)err and LX driver and
immediately restarts the
start-up sequence
External Synchronization Pin - NSYNC
Pin NSYNC can be used to synchronize the LX output pin with
Overvoltage at
VOUT
Over Temperature
on chip
V(VOUT) >
Vt(VOUT)err
Tj > Toff
Disables VDDOUT switch
and LX driver and waits until
output voltage V(VOUT)
drops to Vt(VOUT) to restart
the start-up sequence
Disables VDDOUT switch
and LX driver and waits until
junction temp drops to “Ton”
to restart the start-up
sequence
an external clock signal in the range from 600kHz to 1.4MHz.
A frequency detector monitoring NSYNC enables external
synchronization if f(NSYNC) is higher than about 300kHz. If
the pin is e.g. static high the internal oscillator defines the LX
output frequency and phase. When externally synchronized
all falling edges at LX are timed from the falling edge of the
clock signal applied at NSYNC. The timing of the rising edge
at LX is defined by the boost controller.
Maximum Duty Cycle – LX
The maximum duty cycle Dmax, at which the power FET can
operate defines the upper limit of the regulator output to
input voltage ratio according to the formula: V OUT /V IN = 1/
(1-Dmax). In the ISL97702, Dmax is defined from the
minimum off-time toff(LX)min and the switching frequency.
9
FN7462.0
October 13, 2005
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