参数资料
型号: ISL98002CRZ-EVALZ
厂商: Intersil
文件页数: 10/28页
文件大小: 0K
描述: EVAL BOARD FOR ISL98002CRZ
标准包装: 1
系列: *
18
FN6535.1
December 7, 2009
Input Coupling
Inputs can be either AC-coupled (default) or DC-coupled
(see register 0x05[1]). AC coupling is usually preferred since
it allows video signals with substantial DC offsets to be
accurately digitized. The ISL98002 provides a complete
internal DC-restore function, including the DC restore clamp
(see Figure 5) and programmable clamp timing (registers
0x14, 0x15, 0x16, and 0x23).
When AC-coupled, the DC restore clamp is applied at every
line, a programmable number of pixels after the trailing edge
of HSYNC. If register 0x05[5] = 0 (the default), the clamp will
not be applied while the DPLL is coasting, preventing any
clamp voltage errors from composite sync edges,
equalization pulses, or Macrovision signals.
After the trailing edge of HSYNC, the DC restore clamp is
turned on after the number of pixels specified in the DC
Restore and ABLC Starting Pixel registers (0x14 and
0x15) has been reached. The clamp is applied for the
number of pixels specified by the DC Restore Clamp Width
Register (0x16). The clamp can be applied to the back porch
of the video, or to the front porch (by increasing the DC
Restore and ABLC Starting Pixel registers so all the active
video pixels are skipped).
If DC-coupled operation is desired, the input to the ADC will
be the difference between the input signal (RIN, for example)
and that channel’s ground reference (RGBGND in that
example).
TABLE 3. YUV MAPPING (4:2:2)
INPUT
SIGNAL
ISL98002
INPUT
CHANNEL
ISL98002
OUTPUT
ASSIGNMENT
OUTPUT
SIGNAL
Y
Green
Y0Y1Y2Y3
Pb
Blue
driven low
Pr
Red
U0V1U2V3
FIGURE 5. VIDEO FLOW (INCLUDING ABLC)
R(GB)IN
CLAMP
GENERATION
R(GB)GND
VIN+
VIN-
DC
RESTORE
CLAMP
DAC
VCLAMP
8-BIT ADC
FIXED
OFFSET
ABLC
OFFSET
CONTROL
REGISTERS
ABLC
FIXED
OFFSET
0X00
TO ABLC
BLOCK
TO OUTPUT
FORMATTER
10
8
AUTOMATIC BLACK LEVEL
COMPENSATION (ABLC) LOOP
DC RESTORATION
INPUT
BANDWIDTH
PGA
BANDWIDTH
CONTROL
8
OFFSET
DAC
ISL98002
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