参数资料
型号: ISP1181BBS,551
厂商: ST-ERICSSON
元件分类: 总线控制器
英文描述: UNIVERSAL SERIAL BUS CONTROLLER, PQCC48
封装: 7 X 7 MM, 0.85 MM HEIGHT, PLASTIC, MO-220, SOT-619-2, HVQFN-48
文件页数: 20/71页
文件大小: 351K
代理商: ISP1181BBS,551
Philips Semiconductors
ISP1181B
Full-speed USB peripheral controller
Product data
Rev. 02 — 07 December 2004
26 of 70
9397 750 13958
Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Remark: If any change is made to an endpoint conguration which affects the
allocated memory (size, enable/disable), the FIFO memory contents of all endpoints
becomes invalid. Therefore, all valid data must be removed from enabled endpoints
before changing the conguration.
Code (Hex): 20 to 2F — write (control OUT, control IN, endpoint 1 to 14)
Code (Hex): 30 to 3F — read (control OUT, control IN, endpoint 1 to 14)
Transaction — write/read 1 byte
12.1.2
Write/Read Device Address
This command is used to set the USB assigned address in the Address Register and
enable the USB device. The Address Register bit allocation is shown in Table 16.
A USB bus reset sets the device address to 00H (internally) and enables the device.
The value of the Address Register (accessible by the micro) is not altered by the bus
reset. In response to the standard USB request Set Address the rmware must issue
a Write Device Address command, followed by sending an empty packet to the host.
The new device address is activated when the host acknowledges the empty packet.
Code (Hex): B6/B7 — write/read Address Register
Transaction — write/read 1 byte
Table 14:
Endpoint Conguration Register: bit allocation
Bit
7
6
5
4
3
2
1
0
Symbol
FIFOEN
EPDIR
DBLBUF
FFOISO
FFOSZ[3:0]
Reset
00000000
Access
R/W
Table 15:
Endpoint Conguration Register: bit description
Bit
Symbol
Description
7
FIFOEN
A logic 1 indicates an enabled FIFO with allocated memory.
A logic 0 indicates a disabled FIFO (no bytes allocated).
6
EPDIR
This bit denes the endpoint direction (0 = OUT, 1 = IN). It also
determines the DMA transfer direction (0 = read, 1 = write).
5
DBLBUF
A logic 1 indicates that this endpoint has double buffering.
4
FFOISO
A logic 1 indicates an isochronous endpoint. A logic 0 indicates
a bulk or interrupt endpoint.
3 to 0
FFOSZ[3:0]
Selects the FIFO size according to Table 5
Table 16:
Address Register: bit allocation
Bit
7
6
5
4
3
2
1
0
Symbol
DEVEN
DEVADR[6:0]
Reset
00000000
Access
R/W
相关PDF资料
PDF描述
ISP1181BBS,518 UNIVERSAL SERIAL BUS CONTROLLER, PQCC48
ISP1181BDGG,112 UNIVERSAL SERIAL BUS CONTROLLER, PDSO48
ISP1183BS,157 UNIVERSAL SERIAL BUS CONTROLLER, PQCC32
ISP1362EE,551 UNIVERSAL SERIAL BUS CONTROLLER, PBGA64
ISP1520BD,557 UNIVERSAL SERIAL BUS CONTROLLER, PQFP64
相关代理商/技术参数
参数描述
ISP1181BBSGE 功能描述:IC USB CNTRLR FULL-SPD 48-HVQFN RoHS:是 类别:集成电路 (IC) >> 接口 - 控制器 系列:- 标准包装:4,900 系列:- 控制器类型:USB 2.0 控制器 接口:串行 电源电压:3 V ~ 3.6 V 电流 - 电源:135mA 工作温度:0°C ~ 70°C 安装类型:表面贴装 封装/外壳:36-VFQFN 裸露焊盘 供应商设备封装:36-QFN(6x6) 包装:* 其它名称:Q6396337A
ISP1181BBS-S 功能描述:IC USB HOST CTRL FLL-SPD 48HVQFN RoHS:是 类别:集成电路 (IC) >> 接口 - 控制器 系列:- 标准包装:4,900 系列:- 控制器类型:USB 2.0 控制器 接口:串行 电源电压:3 V ~ 3.6 V 电流 - 电源:135mA 工作温度:0°C ~ 70°C 安装类型:表面贴装 封装/外壳:36-VFQFN 裸露焊盘 供应商设备封装:36-QFN(6x6) 包装:* 其它名称:Q6396337A
ISP1181BBS-T 功能描述:USB 接口集成电路 USB 1.1 DEVICE CONTROLLER RoHS:否 制造商:Cypress Semiconductor 产品:USB 2.0 数据速率: 接口类型:SPI 工作电源电压:3.15 V to 3.45 V 工作电源电流: 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:WLCSP-20
ISP1181BBSUM 功能描述:IC USB HOST CTRL FLL-SPD 48HVQFN RoHS:是 类别:集成电路 (IC) >> 接口 - 控制器 系列:- 标准包装:4,900 系列:- 控制器类型:USB 2.0 控制器 接口:串行 电源电压:3 V ~ 3.6 V 电流 - 电源:135mA 工作温度:0°C ~ 70°C 安装类型:表面贴装 封装/外壳:36-VFQFN 裸露焊盘 供应商设备封装:36-QFN(6x6) 包装:* 其它名称:Q6396337A
ISP1181BDGG 功能描述:USB 接口集成电路 USB CNTRLR FULL-SPD RoHS:否 制造商:Cypress Semiconductor 产品:USB 2.0 数据速率: 接口类型:SPI 工作电源电压:3.15 V to 3.45 V 工作电源电流: 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:WLCSP-20