参数资料
型号: ISP1520BD,557
厂商: NXP SEMICONDUCTORS
元件分类: 总线控制器
英文描述: UNIVERSAL SERIAL BUS CONTROLLER, PQFP64
封装: 10 X 10 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT-314-2, LQFP-64
文件页数: 8/54页
文件大小: 288K
代理商: ISP1520BD,557
ISP1520_4
Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Product data sheet
Rev. 04 — 28 April 2006
15 of 53
Philips Semiconductors
ISP1520
Hi-Speed USB hub controller
8.2.1.2
Data transfer
The master initiates each data transfer using a START condition and terminates it by
generating a STOP condition. To facilitate the next byte transfer, each byte of data must be
acknowledged by the receiver. The acknowledgment is done by pulling the SDA line LOW
on the ninth bit of the data. An extra clock pulse must be generated by the master to
accommodate this bit.
For details on the operation of the bus, refer to
The I2C-bus specication.
8.2.1.3
I2C-bus address
The address of the ISP1520 is given in Table 10.
8.2.2 Architecture of congurable hub descriptors
The congurable hub descriptors can be masked in the internal ROM memory; see
Figure 7. These descriptors can also be supplied from an external EEPROM or a
microcontroller. The ISP1520 implements both the master and slave I2C-bus controllers.
The information from the external EEPROM or the microcontroller is transferred into the
internal RAM during the power-on reset. A signature word is used to identify correct
descriptors. If the signature matches, the content of the RAM is chosen instead of the
ROM.
Table 10.
I2C-bus slave address
Bit
MSB
Slave address
LSB
Write
A7
A6
A5
A4
A3
A2
A1
Value
00110100
The I2C-bus cannot be shared between the EEPROM and the external microcontroller.
Fig 7.
Congurable hub descriptors
mld711
MICROCONTROLLER
SERIAL EEPROM
MASTER/SLAVE
I2C-BUS INTERFACE
signature
match
RAM
(256 B)
DESCRIPTOR
GENERATOR
INTERFACE
ROM
(256 B)
MUX
HUB CORE
I2C-bus
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