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参数资料
| 型号： | ISPLSI 1016-90LT44 |
| 厂商： | Lattice Semiconductor Corporation |
| 文件页数： | 11/17页 |
| 文件大小： | 0K |
| 描述： | IC PLD ISP 32I/O 12NS 44TQFP |
| 标准包装： | 160 |
| 系列： | ispLSI® 1000 |
| 可编程类型： | 系统内可编程 |
| 最大延迟时间 tpd(1)： | 12.0ns |
| 电压电源 - 内部： | 4.75 V ~ 5.25 V |
| 逻辑元件/逻辑块数目： | 16 |
| 门数： | 2000 |
| 输入/输出数： | 32 |
| 工作温度： | 0°C ~ 70°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 44-TQFP |
| 供应商设备封装： | 44-TQFP（10x10） |
| 包装： | 托盘 |
| 其它名称： | ISPLSI1016-90LT44 |
Specifications ispLSI 1016
2
Functional Block Diagram
Figure 1. ispLSI 1016 Functional Block Diagram
I/O 0
I/O 1
I/O 2
I/O 3
IN 3
MODE/IN 2
I/O 6
I/O 7
I/O 8
I/O 9
I/O 10
I/O 11
I/O 12
I/O 13
I/O 14
I/O 15
I/O 31
I/O 30
I/O 29
I/O 28
I/O 27
I/O 26
I/O 25
I/O 24
I/O 23
I/O 22
I/O 21
I/O 20
I/O 19
I/O 18
I/O 17
I/O 16
SDI/IN 0
SDO/IN 1
I/O 4
I/O 5
SCLK/Y2
ispEN
Global
Routing
Pool
(GRP)
CLK 0
CLK 1
CLK 2
IOCLK 0
IOCLK 1
Clock
Distribution
Network
A0
A1
A2
A3
A4
A5
A6
A7
B7
B6
B5
B4
B3
B2
B1
B 0
Output
Routing
Pool
(ORP)
Generic
Logic Blocks
(GLBs)
Megablock
Output
Routing
Pool
(ORP)
Input
Bus
lnput
Bus
*Note: Y1 and RESET
are multiplexed
on the same pin
Y0
Y1/RESET*
0139B(1a)-isp.eps
The device also has 32 I/O cells, each of which is directly
connected to an I/O pin. Each I/O cell can be individually
programmed to be a combinatorial input, registered in-
put, latched input, output or bi-directional I/O pin with
3-state control.
Additionally, all outputs are polarity
selectable, active high or active low. The signal levels are
TTL compatible voltages and the output drivers can
source 4 mA or sink 8 mA.
Eight GLBs, 16 I/O cells, two dedicated inputs and one
ORP are connected together to make a Megablock (see
figure 1). The outputs of the eight GLBs are connected to
a set of 16 universal I/O cells by the ORP. The ispLSI
1016 device contains two of these Megablocks.
The GRP has as its inputs the outputs from all of the GLBs
and all of the inputs from the bi-directional I/O cells. All of
these signals are made available to the inputs of the
GLBs. Delays through the GRP have been equalized to
minimize timing skew.
Clocks in the ispLSI 1016 device are selected using the
Clock Distribution Network. Three dedicated clock pins
(Y0, Y1 and Y2) are brought into the distribution network,
and five clock outputs (CLK 0, CLK 1, CLK 2, IOCLK 0
and IOCLK 1) are provided to route clocks to the GLBs
and I/O cells. The Clock Distribution Network can also be
driven from a special clock GLB (B0 on the ispLSI 1016
device). The logic of this GLB allows the user to create an
internal clock from a combination of internal signals
within the device.
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相关代理商/技术参数 |
参数描述 |
|---|---|
| ispLSI1016-90LT44 | 功能描述:CPLD - 复杂可编程逻辑器件 USE ispMACH 4000V RoHS:否 制造商:Lattice 系列: 存储类型:EEPROM 大电池数量:128 最大工作频率:333 MHz 延迟时间:2.7 ns 可编程输入/输出端数量:64 工作电源电压:3.3 V 最大工作温度:+ 90 C 最小工作温度:0 C 封装 / 箱体:TQFP-100 |
| ISPLSI1016E | 制造商:LATTICE 制造商全称:Lattice Semiconductor 功能描述:In-System Programmable High Density PLD |
| ISPLSI1016E_02 | 制造商:LATTICE 制造商全称:Lattice Semiconductor 功能描述:In-System Programmable High Density PLD |
| ISPLSI1016E_06 | 制造商:LATTICE 制造商全称:Lattice Semiconductor 功能描述:In-System Programmable High Density PLD |
| ISPLSI1016E100LJ | 制造商:LATTICE 制造商全称:Lattice Semiconductor 功能描述:In-System Programmable High Density PLD |
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