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参数资料
| 型号： | ISPLSI 1016E-80LJN |
| 厂商： | Lattice Semiconductor Corporation |
| 文件页数： | 2/13页 |
| 文件大小： | 0K |
| 描述： | IC PLD ISP 32I/O 80MHZ 44PLCC |
| 标准包装： | 26 |
| 系列： | ispLSI® 1000E |
| 可编程类型： | 系统内可编程 |
| 最大延迟时间 tpd(1)： | 15.0ns |
| 电压电源 - 内部： | 4.75 V ~ 5.25 V |
| 逻辑元件/逻辑块数目： | 16 |
| 门数： | 2000 |
| 输入/输出数： | 32 |
| 工作温度： | 0°C ~ 70°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 44-LCC（J 形引线） |
| 供应商设备封装： | 44-PLCC（16.58x16.58） |
| 包装： | 管件 |
| 其它名称： | 220-1586-5 ISPLSI 1016E-80LJN-ND ISPLSI1016E-80LJN |
10
Specifications ispLSI 1016E
USE
ispLSI
1016EA
FOR
NEW
DESIGNS
Input - This pin performs two functions. When ispEN is logic low, it functions
as an input pin to load programming data into the device. It is a dedicated
input pin when ispEN is logic high.SDI/IN0 also is used as one of the two
control pins for the isp state machine.
Dedicated Clock input. This clock input is connected to one of the clock
inputs of all the GLBs on the device.
This pin performs two functions:
Input - Dedicated in-system programming enable input pin. This pin is
brought low to enable the programming mode. The MODE, SDI, SDO and
SCLK controls become active.
This is a dual function pin. It can be used either as Global Output Enable for
all I/O cells or it can be used as a dedicated input pin.
Input/Output Pins - These are the general purpose I/O pins used by the logic
array.
NAME
Table 2-0002C-16-isp
DESCRIPTION
I/O 0 - I/O 3
I/O 4 - I/O 7
I/O 8 - I/O 11
I/O 12 - I/O 15
I/O 16 - I/O 19
I/O 20 - I/O 23
I/O 24 - I/O 27
I/O 28 - I/O 31
GOE 0/IN 32
Y1/RESET
Y0
SDI/IN 01
ispEN
MODE/IN 21
Input - This pin performs two functions. When ispEN is logic low, it functions
as a pin to control the operation of the isp state machine. It is a dedicated
input pin when ispEN is logic high.
GND
Vcc
VCC
- Dedicated clock input. This clock input is brought into the Clock
Distribution Network, and can optionally be routed to any GLB and/or
I/O cell on the device.
Output/Input - This pin performs two functions. When ispEN is logic low, it
functions as an output pin to read serial shift register data. It is a dedicated
input pin when ispEN is logic high.
SDO/IN 11
Input - This pin performs two functions. When ispEN is logic low, it
functions as a clock pin for the Serial Shift Register. It is a dedicated clock
input when ispEN is logic high. This clock input is brought into the Clock
Distribution Network, and can optionally be routed to any GLB and/or I/O
cell on the device.
SCLK/Y21
Ground (GND)
- Active Low (0) Reset pin which resets all of the GLB and I/O registers
in the device.
PLCC
PIN NUMBERS
15,
19,
25,
29,
37,
41,
3,
7,
16,
20,
26,
30,
38,
42,
4,
8,
17,
21,
27,
31,
39,
43,
5,
9,
18,
22,
28,
32,
40,
44,
6,
10
2
35
11
14
13
36
1,
12,
24
33
23
34
1. Pins have dual function capability.
2. Pins have dual function capability which is software selectable.
TQFP
PIN NUMBERS
9,
13,
19,
23,
31,
35,
41,
1,
10,
14,
20,
24,
32,
36,
42,
2,
11,
15,
21,
25,
33,
37,
43,
3,
12,
16,
22,
26,
34,
38,
44,
4
40
29
5
8
7
30
17,
6,
18
27
39
28
Pin Description
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相关代理商/技术参数 |
参数描述 |
|---|---|
| ispLSI1016E-80LJN | 功能描述:CPLD - 复杂可编程逻辑器件 USE ispMACH 4000V RoHS:否 制造商:Lattice 系列: 存储类型:EEPROM 大电池数量:128 最大工作频率:333 MHz 延迟时间:2.7 ns 可编程输入/输出端数量:64 工作电源电压:3.3 V 最大工作温度:+ 90 C 最小工作温度:0 C 封装 / 箱体:TQFP-100 |
| ISPLSI1016E80LJNI | 制造商:LATTICE 制造商全称:Lattice Semiconductor 功能描述:In-System Programmable High Density PLD |
| ispLSI1016E-80LJNI | 功能描述:CPLD - 复杂可编程逻辑器件 USE ispMACH 4000V RoHS:否 制造商:Lattice 系列: 存储类型:EEPROM 大电池数量:128 最大工作频率:333 MHz 延迟时间:2.7 ns 可编程输入/输出端数量:64 工作电源电压:3.3 V 最大工作温度:+ 90 C 最小工作温度:0 C 封装 / 箱体:TQFP-100 |
| ispLSI1016E-80LT | 制造商:Lattice Semiconductor Corporation 功能描述:EE PLD, 18.5 ns, 44 Pin Plastic QFP |
| ISPLSI1016E80LT44 | 制造商:LATTICE 制造商全称:Lattice Semiconductor 功能描述:In-System Programmable High Density PLD |
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