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参数资料
| 型号： | ISPLSI 1024EA-200LT100 |
| 厂商： | Lattice Semiconductor Corporation |
| 文件页数： | 3/13页 |
| 文件大小： | 0K |
| 描述： | IC PLD ISP 48I/O 10NS 100TQFP |
| 标准包装： | 90 |
| 系列： | ispLSI® 1000EA |
| 可编程类型： | 系统内可编程 |
| 最大延迟时间 tpd(1)： | 4.5ns |
| 电压电源 - 内部： | 4.75 V ~ 5.25 V |
| 逻辑元件/逻辑块数目： | 24 |
| 门数： | 4000 |
| 输入/输出数： | 48 |
| 工作温度： | 0°C ~ 70°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 100-LQFP |
| 供应商设备封装： | 100-TQFP（14x14） |
| 包装： | 托盘 |
| 其它名称： | ISPLSI1024EA-200LT100 |
11
Specifications ispLSI 1024EA
USE
ispMA
CH
4A5
FOR
NEW
5V
DESIGNS
Pin Description
Input - Controls the operation of the ISP state machine.
This is a dual function pin. It can be used either as Global Output Enable for all I/O cells or it can be
used as a dedicated input pin.
This is a dual function pin. It can be used either as Global Output Enable for all I/O cells or it can be
used as a dedicated input pin.
Dedicated Clock input. This clock input is brought into the clock distribution network, and can
optionally be routed to any GLB on the device.
Dedicated Clock input. This clock input is connected to one of the clock inputs of all of the GLBs on
the device.
Input/Output Pins - These are the general purpose I/O pins used by the logic array.
NAME
Table 2-0002A/1024EA
DESCRIPTION
I/O 0 - I/O 3
I/O 4 - I/O 7
I/O 8 - I/O 11
I/O 12 - I/O 15
I/O 16 - I/O 19
I/O 20 - I/O 23
I/O 24 - I/O 27
I/O 28 - I/O 31
I/O 32 - I/O 35
I/O 36 - I/O 39
I/O 40 - I/O 43
I/O 44 - I/O 47
Y1
Y0
TMS
Ground (GND)
GND
GOE 0/IN 41
GOE 1/IN 51
Input - Functions as an input pin to load programming data into the device and also used as one of
the two control pins for the ispJTAG state machine.
TDI
TDO
Output - Functions as an output pin to read serial shift register data.
TCK
Input - Functions as a clock pin for the Serial Shift Register.
Active Low (0) Reset pin which resets all of the GLB and I/O registers in the device.
RESET
Dedicated Clock input. This clock input is brought into the clock distribution network, and can
optionally be routed to any GLB and/or any I/O cell on the device.
Y2
Dedicated Clock input. This clock input is brought into the clock distribution network, and can
optionally be routed to any I/O cell on the device.
Y3
1. Pins have dual function capability which is software selectable.
2. NC pins are not to be connected to any active signals, Vcc or GND.
TQFP PIN
NUMBERS
Vcc
VCC
2,
25,
39,
52,
75,
88,
20,
28,
32,
43,
47,
55,
70,
78,
82,
93,
97,
5,
15,
62,
11,
66,
12,
26,
49,
63,
76,
99,
21,
29,
33,
44,
48,
56,
71,
79,
83,
94,
98,
6,
36,
89,
40,
85,
13,
27,
50,
64,
77,
100
22,
30,
34,
45,
53,
57,
72,
80,
84,
95,
3,
7
37,
90
41,
86
NC2
No Connect
Supply voltage for output drivers, 5V or 3.3V.
VCCIO
1,
24,
38,
51,
74,
87,
19,
23,
31,
42,
46,
54,
69,
73,
81,
92,
96,
4,
67
9
68
8
91
18
35
58
17
60
59
14,
61,
10,
65,
16
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相关代理商/技术参数 |
参数描述 |
|---|---|
| ISPLSI1024EA-200LT100 | 功能描述:CPLD - 复杂可编程逻辑器件 RoHS:否 制造商:Lattice 系列: 存储类型:EEPROM 大电池数量:128 最大工作频率:333 MHz 延迟时间:2.7 ns 可编程输入/输出端数量:64 工作电源电压:3.3 V 最大工作温度:+ 90 C 最小工作温度:0 C 封装 / 箱体:TQFP-100 |
| ISPLSI1032 | 制造商:LATTICE 制造商全称:Lattice Semiconductor 功能描述:In-System Programmable High Density PLD |
| ISPLSI1032-50LJ | 制造商:未知厂家 制造商全称:未知厂家 功能描述:Electrically-Erasable Complex PLD |
| ISPLSI1032-60 | 制造商:LATTICE 制造商全称:Lattice Semiconductor 功能描述:In-System Programmable High Density PLD |
| ISPLSI1032-60LG | 制造商:LATTICE 制造商全称:Lattice Semiconductor 功能描述:In-System Programmable High Density PLD |
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