参数资料
型号: ISPLSI 5512VA-70LB388I
厂商: Lattice Semiconductor Corporation
文件页数: 6/28页
文件大小: 0K
描述: IC PLD ISP 288I/O 15NS 388BGA
标准包装: 24
系列: ispLSI® 5000VA
可编程类型: 系统内可编程
最大延迟时间 tpd(1): 15.0ns
电压电源 - 内部: 3 V ~ 3.6 V
逻辑元件/逻辑块数目: 16
宏单元数: 512
门数: 24000
输入/输出数: 288
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 388-BBGA
供应商设备封装: 388-BGA(35x35)
包装: 托盘
其它名称: ISPLSI5512VA-70LB388I
Specifications ispLSI 5512VA
14
Internal Timing Parameters1
Over Recommended Operating Conditions
I/O Buffer
tidcom
22
Input Pad and Buffer, Combinatorial Input
0.7
0.9
1.4
ns
tidreg
23
Input Pad and Buffer, Registered Input
4.7
6.6
9.7
ns
todcom
24
Output Pad and Buffer, Combinatorial Output
2.4
1.7
2.6
ns
todreg
25
Output Pad and Buffer, Registered Output
1.0
2.8
4.6
ns
todz
26
Output Buffer Enable/Disable
1.7
1.7
2.6
ns
tslf
27
Slew Rate Adder, Fast Slew
–0–0–0
ns
tsls
28
Slew Rate Adder, Slow Slew
8.5
10
15
ns
tslfd
29
Programmable Delay Adder, Fast Slew
0.5
0.7
1
ns
tslsd
30
Programmable Delay Adder, Slow Slew
9.5
10.7
16
ns
GLB/Macrocell Delay Register
tmbp
31
Macrocell Register/Latch Bypass
–0–0–0
ns
tmlat
32
Macrocell Latch Delay
1
1.4
2
ns
tmco
33
Macrocell Register/Latch Clock to Output
1.8
–1–1
ns
tmsu
34
Macrocell Register/Latch Setup Time
1
1.1
1.7
ns
tmh
35
Macrocell Register/Latch Hold Time
2.5
3.9
5.3
ns
tmsuce
36
Macrocell Register/Latch CLKEN Setup Time
1
1.4
2
ns
tmhce
37
Macrocell Register/Latch CLKEN Hold Time
1
1.4
2
ns
tmrst
38
Macrocell Register/Latch Set/Reset Time
1.8
1.4
2
ns
tftog
39
Toggle Flip-Flop Feedback
1
1.3
2
ns
AND Array
tandhs
40
AND Array, High Speed Mode
–3–4–6
ns
tandlp
41
AND Array, Low Power Mode
5
6.6
10
ns
PTSA
t5ptcom
42
5 Product Term Bypass, Combinatorial
0.7
1.4
2
ns
t5ptreg
43
5 Product Term Bypass, Registered
1
1.7
2.3
ns
t5ptxcom
44
5 Product Term XOR, Combinatorial
2.5
3.6
5
ns
t5ptxreg
45
5 Product Term XOR, Registered
2.3
2.2
3.3
ns
tptsacom
46
Product Term Sharing Array, Combinatorial
3
4.1
6
ns
tptsareg
47
Product Term Sharing Array, Registered
2
2.7
4.3
ns
PTSA Controls
tpck
48
Product Term Clock Delay
0.5
0.7
1
ns
tpcken
49
Product Term CLKEN Delay
1
1.4
2
ns
tscken
50
Shared Product Term CLKEN Delay
1
1.4
2
ns
tsck
51
Shared Product Term Clock Delay
0.5
0.7
1
ns
tptsacken
52
Product Term Sharing Array CLKEN Delay
2.0
2.4
4
ns
tsrst
53
Shared Product Term Set/Reset Delay
2.5
3.4
5
ns
tprst
54
Product Term Set/Reset Delay
1.5
–2–3
ns
tpoe
55
Product Term Output Enable/Disable
2.9
3.4
5
ns
tgpoe
56
Global PT Output Enable/Disable
13.1
15.4
17
ns
-110
-100
-70
MIN
MAX MIN
MAX
UNIT
PARAM
#2
DESCRIPTION
1. Internal Timing Parameters are not tested and are for reference only.
Timing Rev 4.0
Refer to Timing Model in this data sheet for further details.
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