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参数资料
| 型号： | JCLGLMUT-155.52MHZ |
| 厂商： | VECTRON INTERNATIONAL |
| 元件分类： | XO, clock |
| 英文描述： | VCXO, CLOCK, 155.52 MHz, PECL OUTPUT |
| 封装： | HERMETICALLY SEALED, CERAMIC, SO-6 |
| 文件页数： | 3/8页 |
| 文件大小： | 113K |
| 代理商： | JCLGLMUT-155.52MHZ |
J-Type Voltage Controlled Crystal Oscillator
Vectron International 166 Glover Avenue, Norwalk, CT 06856 Tel: 1-88-VECTRON-1 Fax: 1-888-FAX-VECTRON
CMOS Output Option
3
Output Test Conditions (25±5°C) for 5 volt devices.
For 3.3V use 15pF cap only, no resistors needed.
Threshold = 1.4 volts for TTL
and 50% for CMOS
Figure 1
Output Wave Form
Figure 2
Output Test Conditions
1.024
1.544
2.000
2.048
3.088
3.580
3.686
4.000
4.032
4.096
4.434
5.000
6.144
6.176
6.312
6.400
8.000
8.192
8.448
10.000
12.000
12.288
12.352
13.000
14.318
15.360
15.440
16.000
16.384
18.432
19.44
20.000
20.480
24.000
24.576
24.704
27.000
30.000
32.000
32.768
34.368
35.328
38.880
40.000
40.960
44.736
50.000
51.840
52.000
65.536
77.760
155.5201
Standard Frequencies, in MHz, for CMOS output option
Ordering Information for the CMOS output option (add frequency)4
J
6 pin
C
5V±10%
U
VCXO G
±50
C
0/70
A
TTL/
T Tri State
N
Standard
Ceramic
CMOS
on pin 2
SOJ
45/55%1
D 3.3V±10% L
±10%
N
±80
L
-40/85
J
CMOS
linear
45/55%2
VCXO
H
±100
K
CMOS
40/60%3
Package
Supply
VCXO
APR
Operating
Output/Duty
Tri-State
Specials
Voltage
Type
(ppm)
Temp.
Cycle
(°C)
Min/Max
1. Output is CMOS and symmetry is tested at TTL and CMOS thresholds.
2. Output is CMOS and symmetry is tested at CMOS threshold. This option is used for 3.3 V operation.
3. Output is CMOS and symmetry is tested at CMOS thresholds. This option is required for 3.3V, frequencies >51.840MHz.
4. Note: Not all combinations are possible.
Example: JDUGCKTN @ 77.76 MHz = 3.3 volt, VCXO@77.760, ±50 ppm APR, 0/70°C, 40/60% Symmetry,
CMOS, Tri-State on pin 2.
1. Uses a PLL multiplier, jitter is 25ps rms typical vs 3ps rms typical for a HFF (High Frequency Fundemental) design. Available with 5 Vdc input only.
Other frequencies available upon request.
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