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参数资料
| 型号： | JDLFCMUN170 |
| 厂商： | VECTRON INTERNATIONAL |
| 元件分类： | VCXO, clock |
| 英文描述： | VCXO, CLOCK, 170 MHz, PECL OUTPUT |
| 封装： | ROHS COMPLIANT, HERMETIC SEALED, J-LEADE, CERAMIC, SOJ-6 |
| 文件页数： | 3/10页 |
| 文件大小： | 200K |
| 代理商： | JDLFCMUN170 |
J-Type Voltage Controlled Crystal Oscillator
Vectron International 267 Lowell Rd. Hudson, NH 03051
Tel:1-88-VECTRON-1
e-mail vectron@vectron.com
2
Table 1. Pin Out Information for the CMOS output Option
Pin
Symbol
Function
1
VC
VCXO Control Voltage
2
Tri-State
1
TTL logic low disables output.
TTL logic high, or no connect, enables output.
3
GND
Case and Electrical Ground
4
Output
VCXO Output
5
CMOS/TTL
select
1,2
TTL logic low optimizes symmetry for CMOS.
TTL logic high, or NC, optimizes symmetry for TTL
6
VCC
Power Supply Voltage (5.0 V or 3.3 V
±10%)
1. Standard option. Tri-State can be connected to pin 5 and CMOS/TTL select would be on pin 2.
2. Output is HCMOS. For frequencies >12MHz, this option optimizes symmetry for either CMOS or TTL thresholds. Ground this pin
for frequencies < 12MHz.
Table 2. Electrical Performance @ 25
°C for the CMOS output option
Parameter
Symbol
Minimum
Typical
Maximum
Units
Supply Voltage
1, +5 volt option
+3.3 volt option
4.5
3.0
5.0
3.3
5.5
3.6
V
Supply Current
10mA + 0.25mA per MHz, typical
Center Frequency, see ordering information
FN
1.024
77.760
MHz
Operating Temperature, see ordering info
TOP
0/70, -40/85
°C
Absolute Pull Range over the operating
temperature range, aging and power supply
Vc= 0.5 to 4.5 or 0.3 to 3.0 V
see ordering information for options
APR
±50 to ±100
ppm
Gain Transfer
(Frequency vs. Control Voltage)
KV
Positive
Output Level High
2
VOH
0.8*Vcc
-
V
Output Level Low
2
VOL
-
0.1*Vcc
V
Output Rise/Fall Time
2
tR/ tF
5
ns
Duty Cycle
3, see ordering info
SYM
45/55 or 40/60
%
Input Leakage
IL
±1
uA
Control Voltage Modulation Bandwidth
BW
-
10
-
kHz
RMS Jitter, 77.760MHz
3
ps
RMS Jitter, 77.760MHz, 12kHz to 20MHz
<0.5
ps
Maximum Control Voltage
0
VDD
Maximum Supply Voltage
7
V
Storage Temperature
TS
-55
-
125
°C
Soldering Temp./Time
TLS
-
240/10
°C/s
1. Power supply bypass is required and a 0.1uF in parallel with a 0.01uF high frequency capacitor is recommended
.
2. Figure 1 defines these parameters. Figure 2 illustrates the load used to test devices.
3. Duty cycle is defined as on-time versus period at 1.4 V for TTL, and 2.5 V for CMOS (5volt supply) and at 1.65 V for CMOS (3.3
volt operation)
Figure 1. Output Waveform
Figure 2. Output Test Conditions (25
±5°C)
for 5 volt devices, 15pF cap only for 3.3V.
80
%
50%
20
%
TF
TR
Period
On Time
+
-
+
-
I
C
V
C
4
3
.1
F
.01
F
15pF
25
6
1
I
DD
650
Ohm
1.8k
Ohm
V
DD
65
4
3
2
1
TOP VIEW
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