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参数资料
| 型号： | K3N7C1000M-TC15 |
| 元件分类： | PROM |
| 英文描述： | 4M X 16 MASK PROM, 150 ns, PDSO44 |
| 封装： | 0.400 INCH, TSOP2-44 |
| 文件页数： | 3/4页 |
| 文件大小： | 71K |
| 代理商： | K3N7C1000M-TC15 |
K3N7C1000M-TC
CMOS MASK ROM
TEST CONDITIONS
Item
Value
Input Pulse Levels
0.6V to 2.4V
Input Rise and Fall Times
10ns
Input and Output timing Levels
0.8V and 2.0V
Output Loads
1 TTL Gate and C
L
=100pF
AC CHARACTERISTICS
(
T
A
=
0
to 70
°
C,
V
CC
=5V
±
10%, unless otherwise noted.)
READ CYCLE
Item
Symbol
K3N7C1000M-TC12
K3N7C1000M-TC15
Unit
Min
Max
Min
Max
Read Cycle Time
t
RC
120
150
ns
Chip Enable Access Time
t
ACE
120
150
ns
Address Access Time
t
AA
120
150
ns
Output Enable Access Time
t
OE
60
70
ns
Output or Chip Disable to
Output High-Z
t
DF
20
30
ns
Output Hold from Address Change
t
OH
0
0
ns
TIMING DIAGRAM
READ
NOTES :
*1. Byte Mode only. A
-1
is Least Significant Bit Address.(BHE = V
IL
)
*2. Word Mode only.(BHE=V
IH
)
*3. t
DF
is defined as the time at which the outputs achieve the open circuit condition and is not referenced to V
OH
or V
OL
level.
ADD
A
0
~A
21
A
-1(*1)
CE
OE
D
OUT
D
0
~D
7
D
8
~D
15(*2)
ADD1
ADD2
VALID DATA
VALID DATA
t
OH
t
DF(*3)
t
RC
t
ACE
t
OE
t
AA
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