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参数资料
| 型号： | K7I643684M-FC20 |
| 元件分类： | SRAM |
| 英文描述： | 2M X 36 DDR SRAM, 0.45 ns, PBGA165 |
| 封装： | 15 X 17 MM, 1 MM PITCH, FBGA-165 |
| 文件页数： | 13/18页 |
| 文件大小： | 190K |
| 代理商： | K7I643684M-FC20 |
2Mx36 & 4Mx18 & 8Mx8 DDRII CIO b4 SRAM
- 4 -
Rev 0.1
Mar. 2003
K7I643684M
K7I641884M
K7I640884M
Preliminary
PIN CONFIGURATIONS(TOP VIEW) K7I641884M(2Mx18)
Notes: 2. BW0 controls write to DQ0:DQ8 and BW1 controls write to DQ9:DQ17.
1
2
3
4
5
6
7
8
9
10
11
A
CQ
SA
R/ W
BW 1
K
NC
LD
SA
CQ
B
NC
DQ9
NC
SA
NC
K
BW0
SA
NC
DQ8
C
NC
VSS
SA
SA0
SA1
VSS
NC
DQ7
NC
D
NC
DQ10
VSS
NC
E
NC
DQ11
VDDQ
VSS
V DDQ
NC
DQ6
F
NC
DQ12
NC
VDDQ
VDD
VSS
VDD
V DDQ
NC
DQ5
G
NC
DQ13
VDDQ
VDD
VSS
VDD
V DDQ
NC
H
Doff
VREF
VDDQ
VDD
VSS
VDD
V DDQ
VDDQ
VREF
ZQ
J
NC
VDDQ
VDD
VSS
VDD
V DDQ
NC
DQ4
NC
K
NC
DQ14
VDDQ
VDD
VSS
VDD
V DDQ
NC
DQ3
L
NC
DQ15
NC
VDDQ
VSS
V DDQ
NC
DQ2
M
NC
VSS
NC
DQ1
NC
N
NC
DQ16
VSS
SA
VSS
NC
P
NC
DQ17
SA
C
SA
NC
DQ0
R
TDO
TCK
SA
C
SA
TMS
TDI
PIN NAME
Notes: 1. C, C, K or K cannot be set to V REF voltage.
2. When ZQ pin is directly connected to VDD output impedance is set to minimum value and it cannot be connected to ground or left unconnected.
3. Not connected to chip pad internally.
SYMBOL
PIN NUMBERS
DESCRIPTION
NOTE
K, K
6B, 6A
Input Clock
C, C
6P, 6R
Input Clock for Output Data
1
CQ, CQ
11A, 1A
Output Echo Clock
Doff
1H
DLL Disable when low
SA0,SA1
6C,7C
Burst Count Address Inputs
SA
2A,3A,9A,10A,4B,8B,5C,5N-7N,4P,5P,7P,8P,3R-5R,7R-9R
Address Inputs
DQ0-17
2B,11B,10C,3D,3E,11E,2F,11F,3G,10J,3K,11K,2L,11L
10M,3N,3P,11P
Data Inputs Outputs
R/ W
4A
Read, Write Control Pin, Read active
when high
LD
8A
Synchronous Load Pin, bus Cycle
sequence is to be defined when low
BW0, BW1
7B, 5A
Block Write Control Pin,active when low
VREF
2H,10H
Input Reference Voltage
ZQ
11H
Output Driver Impedance Control Input
2
VDD
5F,7F,5G,7G,5H,7H,5J,7J,5K,7K
Power Supply ( 1.8 V )
VDDQ
4E,8E,4F,8F,4G,8G,3H,4H,8H,9H,4J,8J,4K,8K,4L,8L
Output Power Supply ( 1.5V or 1.8V )
V SS
2A,4C,8C,4D-8D,5E-7E,6F,6G,6H,6J,6K,5L-7L,4M-8M,4N,8N
Ground
TMS
10R
JTAG Test Mode Select
TDI
11R
JTAG Test Data Input
TCK
2R
JTAG Test Clock
TDO
1R
JTAG Test Data Output
NC
7A,1B,3B,5B,9B,10B,1C,2C,3C,9C,11C,1D,2D,9D,10D,11D
1E,2E,9E,10E,1F,3F,9F,10F,1G,2G,9G,10G,11G
1J,2J,3J,9J,11J,1K,2K,9K,10K,1L,3L,9L,10L
1M,2M,3M,9M,11M,1N,2N,9N,10N,11N,1P,2P,9P,10P
No Connect
3
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