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| 型号： | KIT34844AEPEVBE |
| 厂商： | Freescale Semiconductor |
| 文件页数： | 57/62页 |
| 文件大小： | 0K |
| 描述： | KIT EVAL BOARD 10CH LED BACKLGHT |
| 标准包装： | 1 |
| 系列： | * |
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LAYOUT GUIDELINES
LAYOUT GUIDELINES
RECOMMENDED STACK-UP
The following table shows the recommended layer stack-
up for the signals to have good shielding and Thermal
Dissipation.
Table 16. Layer Stacking Recommendations
SWITCHING NODE (SWA & SWB)
The components associated to this node must be placed
as close as possible to each other to keep the switching loop
small enough so that it does not contaminate other signals.
However, care must be taken to ensure the copper traces
used to connect these components together on this node are
Layer 1 (Top)
Layer 2 (Inner 1)
Layer 3(Inner 2)
Layer 4 (Bottom)
Stack-Up
Signal
Ground
Signal
Ground
capable to handle the necessary current and voltage.
As a reference, a 10 mils trace with a thickness of 1.0 oz.
of copper is capable of handling one ampere.
Traces for connecting the inductor, input and output caps
should be as wide and short as possible to avoid adding
inductance or resistance to the loop. The placement of these
components should be selected far away from sensitive
signals like compensation, feedback and internal regulators
DECOUPLING CAPS
It is recommended to place decoupling caps of 100 pf at
the beginning and at the end of any power signal traces to
filter high frequency noise.
Decoupling caps of 100 pf should be also placed at the
end of any long trace to cancel antenna effects on it.
These caps should be located as closed as possible to the
point to be decoupled and the connection to GND should be
as short as possible.
SM-BUS/I 2 C COMMUNICATION AND CLOCK
SIGNALS (SDA, SCK AND CK)
To avoid contamination of these signals by nearby high
power or high frequency signals, it is a good practice to shield
them with ground planes placed on adjacent layers. Make
sure the ground plane is uniform through the whole signal
trace length.
to avoid power noise coupling.
COMPENSATION COMPONENTS
Components related with COMP pin need to be placed as
close as possible to the pin.
FEEDBACK SIGNAL
The trace of the feedback signal (VOUT) should be routed
perpendicularly or at 45° on a different layer to avoid coupling
noise, preferably between ground or power planes.
I I n n p p u u t t C C a a p p
S S w w i i t t c c h h i i n n g g N N o o d d e e
On State
DO
Signal
Signal
i
C o m p e n s a t t i o n
F F e e e e d d b b a a c c k k
S S i i g g n n a a l l
Off State
O u t p u t t C a p
Ground Planes
Ground Plane
Figure 32. Recommended shielding for critical signals.
Figure 33. Feedback Signal Tracing
These signals shall not run parallel to power signals or
other clock signals in the same routing layer. If they have to
cross or to be routed close to a power signal, it is a good
practice to trace them perpendicularly or at 45° on a different
layer to avoid coupling noise.
34844
Analog Integrated Circuit Device Data
Freescale Semiconductor
57
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