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参数资料
| 型号： | KM68V1002AJ-2000 |
| 元件分类： | SRAM |
| 英文描述： | 128K X 8 STANDARD SRAM, 20 ns, PDSO32 |
| 封装： | 0.400 INCH, PLASTIC, SOJ-32 |
| 文件页数： | 4/8页 |
| 文件大小： | 164K |
| 代理商： | KM68V1002AJ-2000 |
KM68V1002A, KM68V1002AI
CMOS SRAM
PRELIMINARY
Rev 5.0
- 4 -
February 1998
READ CYCLE
NOTE: The above parameters are also guaranteed at industrial temperature range.
Parameter
Symbol
KM68V1002A-12
KM68V1002A-15
KM68V1002A-20
Unit
Min
Max
Min
Max
Min
Max
Read Cycle Time
tRC
12
-
15
-
20
-
ns
Address Access Time
tAA
-
12
-
15
-
20
ns
Chip Select to Output
tCO
-
12
-
15
-
20
ns
Output Enable to Valid Output
tOE
-
6
-
7
-
9
ns
Chip Enable to Low-Z Output
tLZ
3
-
3
-
3
-
ns
Output Enable to Low-Z Output
tOLZ
0
-
0
-
0
-
ns
Chip Disable to High-Z Output
tHZ
0
6
0
7
0
9
ns
Output Disable to High-Z Output
tOHZ
0
6
0
7
0
9
ns
Output Hold from Address Change
tOH
3
-
3
-
3
-
ns
Chip Selection to Power Up Time
tPU
0
-
0
-
0
-
ns
Chip Selection to Power DownTime
tPD
-
12
-
15
-
20
ns
TEST CONDITIONS
NOTE: The above test conditions are also applied at industrial temperature range.
Parameter
Value
Input Pulse Levels
0V to 3V
Input Rise and Fall Times
3ns
Input and Output timing Reference Levels
1.5V
Output Loads
See below
AC CHARACTERISTICS(TA=0 to 70
°C, VCC=3.3±0.3V, unless otherwise noted.)
Output Loads(B)
DOUT
5pF*
319
353
for tHZ, tLZ, tWHZ, tOW, tOLZ & tOHZ
+3.3V
* Including Scope and Jig Capacitance
Output Loads(A)
DOUT
RL = 50
ZO = 50
VL = 1.5V
30pF*
* Capacitive Load consists of all components of the
test environment.
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