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参数资料
| 型号： | KM68V1002CLIT-15 |
| 元件分类： | SRAM |
| 英文描述： | 128K X 8 STANDARD SRAM, 15 ns, PDSO32 |
| 封装： | 0.400 INCH, TSOP2-32 |
| 文件页数： | 8/9页 |
| 文件大小： | 183K |
| 代理商： | KM68V1002CLIT-15 |
KM68V1002C/CL, KM68V1002CI/CLI
CMOS SRAM
PRELIMINARY
Revision 2.0
- 8 -
March 1999
PRELIMINARY
DATA RETENTION CHARACTERISTICS*(TA=0 to 70
°C)
* The above parameters are also guaranteed at industrial temperature range.
Data Retention Characteristic is for L-ver only.
Parameter
Symbol
Test Condition
Min.
Typ.
Max.
Unit
VCC for Data Retention
VDR
CS
≥VCC-0.2V
2.0
-
3.6
V
Data Retention Current
IDR
VCC=3.0V, CS
≥VCC-0.2V
VIN
≥VCC-0.2V or VIN≤0.2V
-
0.4
mA
VCC=2.0V, CS
≥VCC-0.2V
VIN
≥VCC-0.2V or VIN≤0.2V
-
0.3
Data Retention Set-Up Time
tSDR
See Data Retention
Wave form(below)
0
-
ns
Recovery Time
tRDR
5
-
ms
DATA RETENTION WAVE FORM
CS controlled
VCC
3.0V
VIH
VDR
CS
GND
Data Retention Mode
CS
≥VCC - 0.2V
tSDR
tRDR
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