参数资料
型号: KMPC8280CZUQLDA
厂商: Freescale Semiconductor
文件页数: 17/83页
文件大小: 0K
描述: IC MPU PWRQUICC II HIP7 480-TBGA
标准包装: 2
系列: MPC82xx
处理器类型: 32-位 MPC82xx PowerQUICC II
速度: 333MHz
电压: 1.5V
安装类型: 表面贴装
封装/外壳: 480-LBGA
供应商设备封装: 408-TBGA(37.5x37.5)
包装: 托盘
MPC8280 PowerQUICC II Family Hardware Specifications, Rev. 2
24
Freescale Semiconductor
AC Electrical Characteristics
This figure shows signal behavior for all parity modes (including ECC, RMW parity, and standard parity).
Figure 10. Parity Mode Diagram
This figure shows signal behavior in MEMC mode.
Figure 11. MEMC Mode Diagram
NOTE
Generally, all SoC bus and system output signals are driven from the rising
edge of the input clock (CLKin). Memory controller signals, however,
trigger on four points within a CLKin cycle. Each cycle is divided by four
internal ticks: T1, T2, T3, and T4. T1 always occurs at the rising edge, and
T3 at the falling edge, of CLKin. However, the spacing of T2 and T4
depends on the PLL clock ratio selected, as shown in Table 15.
CLKin
DATA bus, ECC, and PARITY mode
Pipeline mode—
DP mode output signal
sp13
sp10
sp14a
sp10
Pipeline mode—
sp10
DP mode input signal
sp14
sp10
DATA bus, ECC, and PARITY mode
DP mode input signal
input signals
sp30
sp33b
sp13a
CLKin
V_CLK
Memory controller signals
sp34/sp30
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