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型号： KMPC8280ZUUPEA
厂商： Freescale Semiconductor
文件页数： 78/83页
文件大小： 0K
描述： IC MPU PWRQUICC II HIP7 480-TBGA
标准包装： 2
系列： MPC82xx
处理器类型： 32-位 MPC82xx PowerQUICC II
速度： 450MHz
电压： 1.5V
安装类型： 表面贴装
封装/外壳： 480-LBGA
供应商设备封装： 408-TBGA（37.5x37.5）
包装： 托盘
MPC8280 PowerQUICC II Family Hardware Specifications, Rev. 2
8
Freescale Semiconductor
Operating Conditions
This table lists recommended operational voltage conditions.
This SoC contains circuitry protecting against damage due to high static voltage or electrical fields;
however, it is advised that normal precautions be taken to avoid application of any voltages higher than
maximum-rated voltages to this high-impedance circuit. Reliability of operation is enhanced if unused
inputs are tied to an appropriate logic voltage level (either GND or VCC).
This figure shows the undershoot and overshoot voltage of the 60x and local bus memory interface of the
SoC. Note that in PCI mode the I/O interface is different.
Figure 2. Overshoot/Undershoot Voltage
2 Caution: VDD/VCCSYN must not exceed VDDH by more than 0.4 V during normal operation. It is recommended that
VDD/VCCSYN should be raised before or simultaneous with VDDH during power-on reset. VDD/VCCSYN may
exceed VDDH by more than 0.4 V during power-on reset for no more than 100 ms.
3 Caution: VDDH can exceed VDD/VCCSYN by 3.3 V during power on reset by no more than 100 mSec. VDDH should
not exceed VDD/VCCSYN by more than 2.5 V during normal operation.
4 Caution: VIN must not exceed VDDH by more than 2.5 V at any time, including during power-on reset.
Table 4. Recommended Operating Conditions1
1 Caution: These are the recommended and tested operating conditions. Proper operation outside of these conditions
is not guaranteed.
Rating
Symbol
Value
Unit
Core supply voltage
VDD
1.45 – 1.60
V
PLL supply voltage
VCCSYN
1.45 – 1.60
V
I/O supply voltage
VDDH
3.135 – 3.465
V
Input voltage
VIN
GND (–0.3) – 3.465
V
Junction temperature (maximum)
Tj
1052
2 Note that for extended temperature parts the range is (-40)
TA
– 105Tj.
°C
Ambient temperature
TA
0–702
°C
GND
GND – 0.3 V
GND – 1.0 V
Not to exceed 10%
GVDD
of tSDRAM_CLK
GVDD + 5%
4 V
VIH
VIL
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