参数资料
型号: KMPC8347VVAJFB
厂商: Freescale Semiconductor
文件页数: 76/99页
文件大小: 0K
描述: IC MPU PWRQUICC II 672-TBGA
标准包装: 2
系列: MPC83xx
处理器类型: 32-位 MPC83xx PowerQUICC II Pro
速度: 533MHz
电压: 1.2V
安装类型: 表面贴装
封装/外壳: 672-LBGA
供应商设备封装: 672-TBGA(35x35)
包装: 托盘
MPC8347EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 12
78
Freescale Semiconductor
Clocking
Addressed by This Document,” for part ordering details and contact your Freescale Sales Representative
or authorized distributor for more information.
Table 59 provides the operating frequencies for the MPC8347EA PBGA under recommended operating
conditions.
Table 58. Operating Frequencies for TBGA
Characteristic1
1 The CLKIN frequency, RCWL[SPMF], and RCWL[COREPLL] settings must be chosen so that the resulting csb_clk, MCLK,
LCLK[0:2], and core_clk frequencies do not exceed their respective maximum or minimum operating frequencies. The value
of SCCR[ENCCM], SCCR[USBDRCM], and SCCR[USBMPHCM] must be programmed so that the maximum internal
operating frequency of the Security core and USB modules does not exceed the respective values listed in this table.
400 MHz
533 MHz
667 MHz
Unit
e300 core frequency (core_clk)
266–400
266–533
266–667
MHz
Coherent system bus frequency (csb_clk)
100–266
100–333
MHz
DDR1 memory bus frequency (MCK)2
2 The DDR data rate is 2x the DDR memory bus frequency.
100–133
100–166.67
MHz
DDR2 memory bus frequency (MCK)3
3 The DDR data rate is 2x the DDR memory bus frequency.
100–133
100–200
MHz
Local bus frequency (LCLKn)4
4 The local bus frequency is 1/2, 1/4, or 1/8 of the lbiu_clk frequency (depending on LCCR[CLKDIV]) which is in turn 1x or 2x
the csb_clk frequency (depending on RCWL[LBIUCM]).
16.67–133
MHz
PCI input frequency (CLKIN or PCI_CLK)
25–66
MHz
Security core maximum internal operating frequency
133
166
MHz
USB_DR, USB_MPH maximum internal operating
frequency
133
166
MHz
Table 59. Operating Frequencies for PBGA
Parameter1
1 The CLKIN frequency, RCWL[SPMF], and RCWL[COREPLL] settings must be chosen so that the resulting csb_clk, MCLK,
LCLK[0:2], and core_clk frequencies do not exceed their respective maximum or minimum operating frequencies. The value
of SCCR[ENCCM], SCCR[USBDRCM], and SCCR[USBMPHCM] must be programmed so that the maximum internal
operating frequency of the Security core and USB modules does not exceed the respective values listed in this table.
266 MHz
333 MHz
400 MHz
Unit
e300 core frequency (core_clk)
200–266
200–333
200–400
MHz
Coherent system bus frequency (csb_clk)
100–266
MHz
DDR1 memory bus frequency (MCK)2
2 The DDR data rate is 2× the DDR memory bus frequency.
100–133
MHz
DDR2 memory bus frequency (MCK)3
100–133
MHz
Local bus frequency (LCLKn)4
16.67–133
MHz
PCI input frequency (CLKIN or PCI_CLK)
25–66
MHz
Security core maximum internal operating frequency
133
MHz
USB_DR, USB_MPH maximum internal operating
frequency
133
MHz
相关PDF资料
PDF描述
KMPC8347EZUAGDB IC MPU PWRQUICC II 672-TBGA
345-010-541-204 CARDEDGE 10POS DUAL .100 GREEN
XF2U-2715-3A CONNECTOR FPC 27POS 0.5MM SMD
KMPC8347EZUAJFB IC MPU PWRQUICC II 672-TBGA
345-010-541-202 CARDEDGE 10POS DUAL .100 GREEN
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