参数资料
型号: KMPC8379ECVRALG
厂商: Freescale Semiconductor
文件页数: 2/117页
文件大小: 0K
描述: IC MPU POWERQUICC II 689-PBGA
标准包装: 2
系列: MPC83xx
处理器类型: 32-位 MPC83xx PowerQUICC II Pro
速度: 667MHz
电压: 1V
安装类型: 表面贴装
封装/外壳: 689-BBGA 裸露焊盘
供应商设备封装: 689-TEPBGA II(31x31)
包装: 托盘
MPC8379E PowerQUICC II Pro Processor Hardware Specifications, Rev. 8
10
Freescale Semiconductor
2.2
Power Sequencing
The device requires its power rails to be applied in a specific sequence in order to ensure proper device
operation. During the power ramp up, before the power supplies are stable and if the I/O voltages are
supplied before the core voltage, there may be a period of time that all input and output pins will actively
be driven and cause contention and excessive current. To avoid actively driving the I/O pins and to
eliminate excessive current draw, apply the core voltages (VDD and AVDD) before the I/O voltages and
assert PORESET before the power supplies fully ramp up. VDD and AVDD must reach 90% of their
nominal value before GVDD, LVDD, and OVDD reach 10% of their value, see the following figure. I/O
voltage supplies—GVDD, LVDD, and OVDD—do not have any ordering requirements with respect to one
another.
Figure 3. Power-Up Sequencing Example
Note that the SerDes power supply (L[1,2]_nVDD) should follow the same timing as the core supply
(VDD).
The device does not require the core supply voltage and I/O supply voltages to be powered down in any
particular order.
3
Power Characteristics
The estimated typical power dissipation for the chip device is shown in this table.
Table 5. Power Dissipation 1
Core Frequency
(MHz)
CSB/DDR Frequency
(MHz)
Sleep Power
at Tj =65°C (W)
Typical Application
at Tj =65°C (W)
Typical Application
at Tj =125°C (W)
Max Application
at Tj =125°C (W)
333
333
1.45
1.9
3.2
3.8
167
1.45
1.8
3.0
3.6
400
400
1.45
2.0
3.3
4.0
266
1.45
1.9
3.1
3.8
t
90%
V
Core Voltage (VDD, AVDD)
I/O Voltage (GVDD, LVDD, and OVDD)
0
0.7 V
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