参数资料
型号: KMPC8543EVUAQG
厂商: Freescale Semiconductor
文件页数: 121/151页
文件大小: 0K
描述: IC MPU PWRQUICC III 783-FCCBGA
标准包装: 2
系列: MPC85xx
处理器类型: 32-位 MPC85xx PowerQUICC III
速度: 1.0GHz
电压: 1.1V
安装类型: 表面贴装
封装/外壳: 783-BBGA,FCBGA
供应商设备封装: 783-FCPBGA(29x29)
包装: 托盘
MPC8548E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 9
Freescale Semiconductor
71
High-Speed Serial Interfaces (HSSI)
to AC-coupling. Its value could be ranged from 140
to 240 depending on the clock driver vendor’s
requirement. R2 is used together with the SerDes reference clock receiver’s 50-
termination resistor to
attenuate the LVPECL output’s differential peak level such that it meets the SerDes reference clock’s
differential input amplitude requirement (between 200 and 800 mV differential peak). For example, if the
LVPECL output’s differential peak is 900 mV and the desired SerDes reference clock input amplitude is
selected as 600 mV, the attenuation factor is 0.67, which requires R2 = 25
Consult a clock driver chip
manufacturer to verify whether this connection scheme is compatible with a particular clock driver chip.
Figure 45. AC-Coupled Differential Connection with LVPECL Clock Driver (Reference Only)
Figure 46 shows the SerDes reference clock connection reference circuits for a single-ended clock driver.
It assumes the DC levels of the clock driver are compatible with the SerDes reference clock input’s DC
requirement.
Figure 46. Single-Ended Connection (Reference Only)
SD_REF_CLK
Clock Driver
100
Differential PWB Trace
SerDes Refer.
CLK Receiver
Clock Driver
CLK_Out
LVPECL CLK Driver Chip
R2
MPC8548E
10 nF
CLK_Out
R2
R1
Clock Driver
50
50
R1
SD_REF_CLK
100
Differential PWB Trace
Clock Driver
CLK_Out
Single-Ended CLK
Driver Chip
MPC8548E
33
Total 50
Assume clock driver’s
output impedance is about 16
50
SerDes Refer.
CLK Receiver
50
50
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