参数资料
型号: KSZ8041MLL
厂商: Micrel Inc
文件页数: 8/65页
文件大小: 0K
描述: TXRX 10/100 3.3V PHY MII 48-LQFP
标准包装: 250
类型: 收发器
驱动器/接收器数: 1/1
规程: MII
电源电压: 3.135 V ~ 3.465 V
安装类型: 表面贴装
封装/外壳: 48-TQFP
供应商设备封装: 48-TQFP(7x7)
包装: 托盘
产品目录页面: 1080 (CN2011-ZH PDF)
其它名称: 576-3502
Micrel, Inc.
KSZ8041TL/FTL/MLL
December 2009
16
M9999-120909-1.2
Pin Number
Pin Name
Type
(1)
Pin Function
23
DUPLEX
Ipu/O
DUPLEX mode
Pull-up (default) = Half Duplex
Pull-down = Full Duplex
During power-up / reset, this pin value is latched into register 0h bit 8 as the Duplex
Mode.
42
(KSZ8041TL)
NWAYEN
Ipu/O
Nway Auto-Negotiation Enable
Pull-up (default) = Enable Auto-Negotiation
Pull-down = Disable Auto-Negotiation
During power-up / reset, this pin value is latched into register 0h bit 12.
If copper mode (FXEN=0), pin strap-in is Nway Auto-Negotiation Enable.
Pull-up (default) = Enable Auto-Negotiation
Pull-down = Disable Auto-Negotiation
During power-up / reset, this pin value is latched into register 0h bit 12.
42
(KSZ8041FTL)
NWAYEN
Ipu/O
If fiber mode (FXEN=1), this pin configuration is always strapped to disable Auto-
Negotiation.
Note:
1. Ipu/O = Input with internal pull-up (40K +/-30%) during power-up/reset; output pin otherwise.
Ipd/O = Input with internal pull-down (40K +/-30%) during power-up/reset; output pin otherwise.
Pin strap-ins are latched during power-up or reset. In some systems, the MAC receive input pins may drive high during
power-up or reset, and consequently cause the PHY strap-in pins on the MII/RMII/SMII signals to be latched high. In this
case, it is recommended to add 1K pull-downs on these PHY strap-in pins to ensure the PHY does not strap-in to
ISOLATE mode, or is not configured with an incorrect PHY Address.
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KSZ8041MNLU TR 功能描述:TXRX PHY 100BASE TX 3.3V 32QFN RoHS:是 类别:集成电路 (IC) >> 接口 - 驱动器,接收器,收发器 系列:- 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:50 系列:- 类型:收发器 驱动器/接收器数:1/1 规程:RS422,RS485 电源电压:4.75 V ~ 5.25 V 安装类型:通孔 封装/外壳:8-DIP(0.300",7.62mm) 供应商设备封装:8-PDIP 包装:管件 产品目录页面:1402 (CN2011-ZH PDF)