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参数资料
| 型号： | KSZ8041NL AM TR |
| 厂商： | Micrel Inc |
| 文件页数： | 8/54页 |
| 文件大小： | 0K |
| 描述： | TXRX PHY 10/100 3.3V 32MLF |
| 标准包装： | 1,000 |
| 类型： | PHY 收发器 |
| 驱动器/接收器数： | 1/1 |
| 规程： | MII，RMII |
| 电源电压： | 3.135 V ~ 3.465 V |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 32-VFQFN 裸露焊盘，32-MLF? |
| 供应商设备封装： | 32-MLF?（5x5） |
| 包装： | 带卷 (TR) |
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Micrel, Inc.
KSZ8041NL/RNL
September 2010
16
M9999-090910-1.4
Pin Description – KSZ8041RNL
Pin Number
Pin Name
Type
(1)
Pin Function
1
GND
Gnd
Ground
2
VDDPLL_1.8
P
1.8V analog VDD
3
VDDA_3.3
P
3.3V analog VDD
4
RX-
I/O
Physical receive or transmit signal (- differential)
5
RX+
I/O
Physical receive or transmit signal (+ differential)
6
TX-
I/O
Physical transmit or receive signal (- differential)
7
TX+
I/O
Physical transmit or receive signal (+ differential)
8
XO
O
Crystal feedback – for 25 MHz crystal
This pin is a no connect if oscillator or external clock source is used.
9
XI
I
Crystal / Oscillator / External Clock Input
25MHz +/-50ppm
10
REXT
I/O
Set physical transmit output current
Connect a 6.49K
Ω resistor in parallel with a 100pF capacitor to ground on this
pin. See KSZ8041RNL reference schematics.
11
MDIO
I/O
Management Interface (MII) Data I/O
This pin requires an external 4.7K
Ω pull-up resistor.
12
MDC
I
Management Interface (MII) Clock Input
This pin is synchronous to the MDIO data interface.
13
PHYAD0
Ipu/O
The pull-up/pull-down value is latched as PHYADDR[0] during power-up / reset.
See “Strapping Options” section for details.
14
PHYAD1
Ipd/O
The pull-up/pull-down value is latched as PHYADDR[1] during power-up / reset.
See “Strapping Options” section for details.
15
RXD1 /
PHYAD2
Ipd/O
RMII Mode:
RMII Receive Data Output[1]
(2)
/
Config Mode:
The pull-up/pull-down value is latched as PHYADDR[2] during
power-up / reset. See “Strapping Options” section for details.
16
RXD0 /
DUPLEX
Ipu/O
RMII Mode:
RMII Receive Data Output[0]
(2)
/
Config Mode:
Latched as DUPLEX (register 0h, bit 8) during power-up /
reset. See “Strapping Options” section for details.
17
VDDIO_3.3
P
3.3V digital VDD
18
CRS_DV /
CONFIG2
Ipd/O
RMII Mode:
Carrier Sense/Receive Data Valid Output /
Config Mode:
The pull-up/pull-down value is latched as CONFIG2 during
power-up / reset. See “Strapping Options” section for details.
19
REF_CLK
O
50MHz Clock Output
This pin provides the 50MHz RMII reference clock output to the MAC.
20
RX_ER /
ISO
Ipd/O
RMII Mode:
RMII Receive Error Output /
Config Mode:
The pull-up/pull-down value is latched as ISOLATE during
power-up / reset. See “Strapping Options” section for details.
21
INTRP
Opu
Interrupt Output: Programmable Interrupt Output
Register 1Bh is the Interrupt Control/Status Register for programming the
interrupt conditions and reading the interrupt status. Register 1Fh bit 9 sets the
interrupt output to active low (default) or active high.
22
NC
O
No connect
23
TX_EN
I
RMII Transmit Enable Input
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相关代理商/技术参数 |
参数描述 |
|---|---|
| KSZ8041NL-EVAL | 功能描述:以太网开发工具 KSZ8041NL Evaluation Board RoHS:否 制造商:Micrel 产品:Evaluation Boards 类型:Ethernet Transceivers 工具用于评估:KSZ8873RLL 接口类型:RMII 工作电源电压: |
| KSZ8041NLI | 制造商:Micrel Inc 功能描述:IC TXRX PHY 10/100 LV/LP 32-MLF*NIC* |
| KSZ8041NLI TR | 功能描述:以太网 IC Physical Layer Transceiver 10/100BASE-T/TX (Lead Free) RoHS:否 制造商:Micrel 产品:Ethernet Switches 收发器数量:2 数据速率:10 Mb/s, 100 Mb/s 电源电压-最大:1.25 V, 3.45 V 电源电压-最小:1.15 V, 3.15 V 最大工作温度:+ 85 C 封装 / 箱体:QFN-64 封装:Tray |
| KSZ8041NLITR | 制造商:Micrel 功能描述:Physical Layer Transceiver 1Ch 100Mbps |
| KSZ8041NLI-TR | 功能描述:1/1 Transceiver Full MII, RMII 32-MLF? (5x5) 制造商:microchip technology 系列:- 包装:剪切带（CT） 零件状态:有效 类型:收发器 协议:MII，RMII 驱动器/接收器数:1/1 双工:全 接收器滞后:- 数据速率:- 电压 - 电源:3.135 V ~ 3.465 V 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:32-VFQFN 裸露焊盘，32-MLF? 供应商器件封装:32-MLF?（5x5） 标准包装:1 |
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