参数资料
型号: KSZ8051MNL TR
厂商: Micrel Inc
文件页数: 7/59页
文件大小: 0K
描述: TXRX PHY 10/T100 3.3V MII 32-QFN
特色产品: KSZ8051/8031/8021 Series
标准包装: 1
类型: PHY 收发器
驱动器/接收器数: 1/1
规程: MII
电源电压: 1.8V,2.5V,3.3V
安装类型: 表面贴装
封装/外壳: 32-VFQFN 裸露焊盘
供应商设备封装: 32-QFN(5x5)
包装: 标准包装
配用: 576-3865-ND - BOARD EVALUATION FOR KSZ8051MNL
其它名称: 576-3777-6
Micrel, Inc.
KSZ8051MNL/RNL
July 2010
15
M9999-070910-1.0
Pin Description – KSZ8051RNL
Pin Number
Pin Name
Type
(1)
Pin Function
1
GND
Gnd
Ground
2
VDD_1.2
P
1.2V core VDD
(power supplied by KSZ8051RNL)
Decouple with 2.2uF and 0.1uF capacitors to ground.
3
VDDA_3.3
P
3.3V analog VDD
4
RXM
I/O
Physical receive or transmit signal (- differential)
5
RXP
I/O
Physical receive or transmit signal (+ differential)
6
TXM
I/O
Physical transmit or receive signal (- differential)
7
TXP
I/O
Physical transmit or receive signal (+ differential)
8
XO
O
Crystal feedback – for 25 MHz crystal
This pin is a no connect if oscillator or external clock source is used.
9
XI
I
25MHz Mode:
25MHz +/-50ppm Crystal / Oscillator / External Clock Input
50MHz Mode:
50MHz +/-50ppm Oscillator / External Clock Input
10
REXT
I
Set physical transmit output current
Connect a 6.49K
Ω resistor-to-ground on this pin.
11
MDIO
I/O
Management Interface (MII) Data I/O
This pin has a weak pull-up, is open drain like, and requires an external 1.0K pull-
up resistor.
12
MDC
I
Management Interface (MII) Clock Input
This clock pin is synchronous to the MDIO data pin.
13
PHYAD0
Ipu/O
The pull-up/pull-down value is latched as PHYADDR[0] at the de-assertion of reset.
See “Strapping Options” section for details.
14
PHYAD1
Ipd/O
The pull-up/pull-down value is latched as PHYADDR[1] at the de-assertion of reset.
See “Strapping Options” section for details.
15
RXD1 /
PHYAD2
Ipd/O
RMII Mode:
RMII Receive Data Output[1]
(2) /
Config Mode:
The pull-up/pull-down value is latched as PHYADDR[2] at the
de-assertion of reset. See “Strapping Options” section for details.
16
RXD0 /
DUPLEX
Ipu/O
RMII Mode:
RMII Receive Data Output[0]
(2) /
Config Mode:
The pull-up/pull-down value is latched as DUPLEX at the
de-assertion of reset. See “Strapping Options” section for details.
17
VDDIO
P
3.3V, 2.5V or 1.8V digital VDD
18
CRS_DV /
CONFIG2
Ipd/O
RMII Mode:
RMII Carrier Sense/Receive Data Valid Output /
Config Mode:
The pull-up/pull-down value is latched as CONFIG2 at the
de-assertion of reset. See “Strapping Options” section for details.
19
REF_CLK /
B-CAST_OFF
Ipd/O
RMII Mode:
25MHz Mode: This pin provides the 50MHz RMII reference clock
output to the MAC. See also XI (pin 9).
50MHz Mode: This pin is a no connect. See also XI (pin 9).
Config Mode:
The pull-up/pull-down value is latched as B-CAST_OFF at the
de-assertion of reset. See “Strapping Options” section for details.
20
RXER /
ISO
Ipd/O
RMII Mode:
RMII Receive Error Output /
Config Mode:
The pull-up/pull-down value is latched as ISOLATE at the
de-assertion of reset. See “Strapping Options” section for details.
21
INTRP /
Ipu/Opu
Interrupt Output: Programmable Interrupt Output
This pin has a weak pull-up, is open drain like, and requires an external 1.0K pull-
up resistor.
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