参数资料
| 型号： | KSZ8695PI |
| 厂商： | Micrel Inc |
| 文件页数： | 18/42页 |
| 文件大小： | 0K |
| 描述： | IC ARM9 W/MMU 5PORT 289-PBGA |
| 标准包装： | 84 |
| 系列： | * |
| 类型： | * |
| 应用： | * |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 289-PBGA |
| 供应商设备封装： | 289-PBGA（19x19） |
| 包装： | 托盘 |
| 产品目录页面： | 1080 (CN2011-ZH PDF) |
| 配用： | 576-1623-ND - BOARD EVALUATION KSZ8695P-MMB |
| 其它名称： | 576-2111 KSZ8695PI-ND |
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Micrel, Inc.
KS8695P
May 2006
25
M9999-051806
Signal Descriptions by Group
Clock and Reset Pins
Pin
Name
I/O Type
(1)
Description
E1
XCLK1/
CPUCLK
I
External Clock In. This signal is used as the source clock for the transmit clock of
the internal MAC and PHY. The clock frequency is 25MHz ±50ppm. The XCLK1
signal is also used as the reference clock signal for the internal PLL to generate the
125MHz internal system clock.
E2
XCLK2
I
External Clock In. Used with XCLK1 pin when another polarity of crystal is needed.
This is unused for a normal clock input.
M15
URTSN/
CPUCLKSEL
O/I
Normal Mode: UART request to send. Active low output.
During reset: CPU clock select. Select CPU clock source. CPUCLKSEL=0 (normal
mode), the internal PLL clock output is used as the CPU clock source.
CPUCLKSEL=1 (factory reserved test signal).
A17
RESETN
I
KS8695P chip reset. Active low input asserted for at least 256 system clock (40ns)
cycles to reset the KS8695P. When in the reset state, all the output pins are tri-
stated and all open drain signals are oating.
U17
WRSTO
O
Watchdog timer reset output. This signal is asserted for at least 200ms if RESETN
is asserted or when the internal watchdog timer expires.
T17
EROEN/
WRSTPLS
O/I
Normal Mode: ROM/SRAM/FLASH and External I/O output enable. Active low.
When asserted, this signal controls the output enable port of the specied device.
During reset: Watchdog timer reset polarity setting. WRSTPLS=0, Active high;
WRSTPLS=1, Active low. No default.
JTAG Interface Pins
Pin
Name
I/O Type
(1)
Description
G14
TCK
I
JTAG test clock.
G15
TMS
I
JTAG test mode select.
F14
TDI
I
JTAG test data in.
F15
TDO
O
JTAG test data out.
F16
TRSTN
I
JTAG test reset. Active low.
WAN Ethernet Physical Interface Pins
Pin
Name
I/O Type
(1)
Description
G1
WANTXP
O
WAN PHY transmit signal + (differential).
G2
WANTXM
O
WAN PHY transmit signal – (differential).
G3
WANRXP
I
WAN PHY receive signal + (differential).
G4
WANRXM
I
WAN PHY receive signal – (differential).
G5
WANFXSD
I
WAN ber signal detect. Signal detect input when the WAN port is operated in
100BASE-FX 100Mb ber mode. See Application Note 10.
Note
:
1. I = Input.
O = Output.
O/I = Output in normal mode; input pin during reset.
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相关代理商/技术参数 |
参数描述 |
|---|---|
| KSZ8695P-MDP-EVAL | 功能描述:网络开发工具 KSZ88695P-MDP Evaluation Board RoHS:否 制造商:Rabbit Semiconductor 产品:Development Kits 类型:Ethernet to Wi-Fi Bridges 工具用于评估:RCM6600W 数据速率:20 Mbps, 40 Mbps 接口类型:802.11 b/g, Ethernet 工作电源电压:3.3 V |
| KSZ8695P-MMB-EVAL | 功能描述:网络开发工具 KSZ8695P-MMB Evaluation Board RoHS:否 制造商:Rabbit Semiconductor 产品:Development Kits 类型:Ethernet to Wi-Fi Bridges 工具用于评估:RCM6600W 数据速率:20 Mbps, 40 Mbps 接口类型:802.11 b/g, Ethernet 工作电源电压:3.3 V |
| KSZ8695PX | 功能描述:网络控制器与处理器 IC Integrated Multi-Port Gateway Solution w/ Single PCI(Lead Free) RoHS:否 制造商:Micrel 产品:Controller Area Network (CAN) 收发器数量: 数据速率: 电源电流（最大值）:595 mA 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:PBGA-400 封装:Tray |
| KSZ8695PX-EVAL | 功能描述:网络开发工具 KSZ8695PX Evaluation Board RoHS:否 制造商:Rabbit Semiconductor 产品:Development Kits 类型:Ethernet to Wi-Fi Bridges 工具用于评估:RCM6600W 数据速率:20 Mbps, 40 Mbps 接口类型:802.11 b/g, Ethernet 工作电源电压:3.3 V |
| KSZ8695X | 功能描述:网络控制器与处理器 IC Integrated Multi-Port Gateway Solution (Lead Free) RoHS:否 制造商:Micrel 产品:Controller Area Network (CAN) 收发器数量: 数据速率: 电源电流（最大值）:595 mA 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:PBGA-400 封装:Tray |
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