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参数资料
| 型号： | KSZ8721SL TR |
| 厂商： | Micrel Inc |
| 文件页数： | 5/33页 |
| 文件大小： | 0K |
| 描述： | IC TXRX PHY 10/100 3.3V 48SSOP |
| 标准包装： | 1 |
| 类型： | 收发器 |
| 驱动器/接收器数： | 1/1 |
| 规程： | IEEE 802 |
| 电源电压： | 3 V ~ 3.6 V |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 48-BSSOP（0.295"，7.50mm 宽） |
| 供应商设备封装： | 48-SSOP |
| 包装： | 标准包装 |
| 产品目录页面： | 1080 (CN2011-ZH PDF) |
| 配用： | 576-1630-ND - BOARD EVALUATION FOR KSZ8721SL |
| 其它名称： | 576-1031-6 |
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May 2004
13
M9999-051704
KS8721BL/SL
Micrel
asserted. For 10BASE-T links, CRS assertion is based on reception of valid preamble, and de-assertion on reception of an
end-of-frame (EOF) marker.
Collision: Whenever the line state is half-duplex and the transmitter and receiver are active at the same time, the KS8721BL/
SL asserts its collision signal, which is asynchronous to any clock.
RMII (Reduced MII) Data Interface
RMII interface specifies a low-pin count, Reduced Media Independent Interface (RMII) intended for use between Ethernet
PHYs and Switch or Repeater ASICs. It is fully compliant with IEEE 802.3u [2].
This interface has the following characteristics:
It is capable of supporting 10Mbps and 100Mbps data rates.
A single clock reference is sourced from the MAC to PHY (or from an external source).
It provides independent 2-bit wide (di-bit) transmit and receive data paths.
It uses TTL signal levels compatible with common digital CMOS ASIC processes.
RMII Signal Definition
Direction
Signal Name
(w/respect to the PHY)
(w/respect to the MAC)
Use
REF_CLK
Input
Input or Output
Synchronous clock reference for receive, transmit and
control interface
CRS_DV
Output
Input
Carrier Sense/Receive Data Valid
RXD[1:0]
Output
Input
Receive Data
TX_EN
Input
Output
Transmit Enable
TXD[1:0]
Input
Output
Transmit Data
RX_ER
Output
Input (Not Required)
Receive Error
Reference Clock (REF_CLK)
REF_CLK is a continuous 50MHz clock that provides the timing reference for CRS_DV, RXD[1:0], TX_EN, TXD[1:0], and
RX_E. REF_CLK is sourced by the MAC or an external source. Switch implementations may choose to provide REF_CLK as
an input or an output depending on whether they provide a REF_CLK output or rely on an external clock distribution device.
Each PHY device must have an input corresponding to this clock but may use a single clock input for multiple PHYs
implemented on a single IC.
Carrier Sense/Receive Data Valid (CRS_DV)
CRS_DV is asserted asynchronously on detection of carrier due to the criteria relevant to the operating mode. That is, in
10BASE-T mode, when squelch is passed or in 100BASE-X mode when 2 noncontiguous zeroes in 10 bits are detected, the
carrier is detected.
Loss-of-carrier results in the de-assertion of CRS_DV synchronous to REF_CLK. As carrier criteria are met, CRS_DV remains
continuously asserted from the first recovered di-bit of the frame through the final recovered di-bit and is negated prior to the
first REF_CLK that follows the final di-bit.
The data on RXD[1:0] is considered valid once CRS_DV is asserted. However, since the assertion of CRS_DV is asynchronous
relative to REF_CLK, the data on RXD[1:0] remains as “00” until proper receive signal decoding takes place (see “Definition
of RXD[1:0] Behavior”).
Receive Data [1:0] (RXD[1:0])
RXD[1:0] transitions synchronously to REF_CLK. For each clock period in which CRS_DV is asserted, RXD[1:0] transfers two
bits of recovered data from the PHY. In some cases (e.g., before data recovery or during error conditions), a predetermined
value for RXD[1:0] is transferred instead of recovered data. RXD[1:0] remains as “00” to indicate idle when CRS_DV is de-
asserted. Values of RXD[1:0] other than “00” when CRS_DV is de-asserted are reserved for out-of-band signalling (to be
defined). Values other than “00” on RXD[1:0] while CRS_DV is de-asserted are ignored by the MAC/repeater. Upon assertion
of CRS_DV, the PHY ensures that RXD[1:0]=00 until proper receive decoding takes place.
Transmit Enable (TX_EN)
Transmit Enable TX_EN indicates that the MAC is presenting di-bits on TXD[1:0] on the RMII for transmission. TX_EN is
asserted synchronously with the first nibble of the preamble and remains asserted while all transmitted di-bits are presented
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相关代理商/技术参数 |
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| KSZ8765CLXCC | 功能描述:Ethernet Switch 10/100 Base-FX/T/TX PHY MII, RMII Interface 80-LQFP (10x10) 制造商:microchip technology 系列:- 包装:托盘 零件状态:有效 协议:以太网 功能:开关 接口:MII，RMII 标准:10/100 Base-FX/T/TX PHY 电压 - 电源:3.3V 电流 - 电源:- 工作温度:0°C ~ 70°C 封装/外壳:80-LQFP 供应商器件封装:80-LQFP（10x10） 标准包装:160 |
| KSZ8765CLXIC | 功能描述:Ethernet Switch 10/100 Base-FX/T/TX PHY MII, RMII Interface 80-LQFP (10x10) 制造商:microchip technology 系列:- 包装:托盘 零件状态:有效 协议:以太网 功能:开关 接口:MII，RMII 标准:10/100 Base-FX/T/TX PHY 电压 - 电源:3.3V 电流 - 电源:- 工作温度:-40°C ~ 85°C 封装/外壳:80-LQFP 供应商器件封装:80-LQFP（10x10） 标准包装:160 |
| KSZ8775CLXCC | 功能描述:Ethernet Controller 10/100 Base-FX/T/TX PHY MII, RMII Interface 80-LQFP (10x10) 制造商:microchip technology 系列:- 包装:托盘 零件状态:有效 协议:以太网 功能:控制器 接口:MII，RMII 标准:10/100 Base-FX/T/TX PHY 电压 - 电源:3.3V 电流 - 电源:- 工作温度:0°C ~ 70°C 封装/外壳:80-LQFP 供应商器件封装:80-LQFP（10x10） 标准包装:160 |
| KSZ8775CLXIC | 功能描述:Ethernet Controller 10/100 Base-FX/T/TX PHY MII, RMII Interface 80-LQFP (10x10) 制造商:microchip technology 系列:- 包装:托盘 零件状态:有效 协议:以太网 功能:控制器 接口:MII，RMII 标准:10/100 Base-FX/T/TX PHY 电压 - 电源:3.3V 电流 - 电源:- 工作温度:-40°C ~ 85°C 封装/外壳:80-LQFP 供应商器件封装:80-LQFP（10x10） 标准包装:160 |
| KSZ8794CNXCC | 功能描述:Ethernet Controller 10/100 Base-T/TX PHY MII, RMII Interface 64-QFN (8x8) 制造商:microchip technology 系列:- 包装:托盘 零件状态:有效 协议:以太网 功能:控制器 接口:MII，RMII 标准:10/100 Base-T/TX PHY 电压 - 电源:3.3V 电流 - 电源:- 工作温度:0°C ~ 70°C 封装/外壳:64-VFQFN 裸露焊盘 供应商器件封装:64-QFN（8x8） 标准包装:260 |
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