参数资料
型号: KSZ8842-16MBL
厂商: Micrel Inc
文件页数: 110/141页
文件大小: 0K
描述: IC MAC CTLR 2PORT ETH 100-LFBGA
标准包装: 260
控制器类型: 以太网开关控制器
接口: PCI
电源电压: 3.1 V ~ 3.5 V
工作温度: 0°C ~ 70°C
安装类型: 表面贴装
封装/外壳: 100-LBGA
供应商设备封装: 100-LFBGA
包装: 托盘
产品目录页面: 1081 (CN2011-ZH PDF)
配用: 576-1635-ND - BOARD EVALUATION KSZ8842-16MVL
576-1634-ND - BOARD EVALUATION KSZ8842-16MQL
其它名称: 576-3076
Micrel, Inc.
KSZ8842-16/32 MQL/MVL/MVLI/MBL
October 2007
70
M9999-102207-1.9
Bank 18 Interrupt Status Register (0x02): ISR
This register contains the status bits for all QMU and other interrupt sources.
When the corresponding enable bit is set, it causes the interrupt pin to be asserted.
This register is usually read by the host CPU and device drivers during interrupt service routine or polling. The register bits
are not cleared when read. The user has to write “1” to clear
Bit
Default Value
R/W
Description
15
0x0
RO
(W1C)
LCIS Link Change Interrupt Status
When this bit is set, it indicates that the link status has changed from link up to link
down, or link down to link up.
This edge-triggered interrupt status is cleared by writing 1 to this bit.
14
0x0
RO
(W1C)
TXIS Transmit Status
When this bit is set, it indicates that the TXQ MAC has transmitted at least a frame on
the MAC interface and the QMU TXQ is ready for new frames from the host.
This edge-triggered interrupt status is cleared by writing 1 to this bit.
13
0x0
RO
(W1C)
RXIS Receive Interrupt Status
When this bit is set, it indicates that the QMU RXQ has received a frame from the
MAC interface and the frame is ready for the host CPU to process.
This edge-triggered interrupt status is cleared by writing 1 to this bit.
12
0x0
RO
Reserved
11
0x0
RO
(W1C)
RXOIS Receive Overrun Interrupt Status
When this bit is set, it indicates that the Receive Overrun status has occurred.
This edge-triggered interrupt status is cleared by writing 1 to this bit.
10
0x0
RO
Reserved
9
0x1
RO
(W1C)
TXPSIE Transmit Process Stopped Status
When this bit is set, it indicates that the Transmit Process has stopped.
This edge-triggered interrupt status is cleared by writing 1 to this bit.
8
0x1
RO
(W1C)
RXPSIE Receive Process Stopped Status
When this bit is set, it indicates that the Receive Process has stopped.
This edge-triggered interrupt status is cleared by writing 1 to this bit.
7
0x0
RO
(W1C)
RXEFIE Receive Error Frame Interrupt Status
When this bit is set, it indicates that the Receive error frame status has occurred.
This edge-triggered interrupt status is cleared by writing 1 to this bit.
6-0
-
RO
Reserved
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