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参数资料
型号： KSZ8895RQI
厂商： Micrel Inc
文件页数： 93/119页
文件大小： 0K
描述： IC 10/100-T 5 PORT SW 128PQFP
标准包装： 66
系列： *
2011-2012 Microchip Technology Inc.
Preliminary
DS41579C-page 75
PIC16(L)F1782/3
7.0
REFERENCE CLOCK MODULE
The reference clock module provides the ability to send
a divided clock to the clock output pin of the device
(CLKR). This module is available in all oscillator config-
urations and allows the user to select a greater range
of clock submultiples to drive external devices in the
application. The reference clock module includes the
following features:
System clock is the source
Available in all oscillator configurations
Programmable clock divider
Output enable to a port pin
Selectable duty cycle
Slew rate control
The reference clock module is controlled by the
CLKRCON register (Register 7-1) and is enabled when
setting the CLKREN bit. To output the divided clock
signal to the CLKR port pin, the CLKROE bit must be
set. The CLKRDIV<2:0> bits enable the selection of 8
different clock divider options. The CLKRDC<1:0> bits
can be used to modify the duty cycle of the output
clock(1). The CLKRSLR bit controls slew rate limiting.
7.1
Slew Rate
The slew rate limitation on the output port pin can be
disabled. The slew rate limitation is removed by
clearing the CLKRSLR bit in the CLKRCON register.
7.2
Effects of a Reset
Upon any device Reset, the reference clock module is
disabled. The user’s firmware is responsible for
initializing the module before enabling the output. The
registers are reset to their default values.
7.3
Conflicts with the CLKR Pin
There are two cases when the reference clock output
signal cannot be output to the CLKR pin, if:
LP, XT or HS Oscillator mode is selected.
CLKOUT function is enabled.
7.3.1
OSCILLATOR MODES
If LP, XT or HS oscillator modes are selected, the
OSC2/CLKR pin must be used as an oscillator input pin
and the CLKR output cannot be enabled. See
Section 6.2 “Clock Source Types”for more informa-
tion on different oscillator modes.
7.3.2
CLKOUT FUNCTION
The CLKOUT function has a higher priority than the ref-
erence clock module. Therefore, if the CLKOUT func-
tion is enabled by the CLKOUTEN bit in Configuration
Words, FOSC/4 will always be output on the port pin.
Reference Section 4.0 “Device Configuration” for
more information.
7.4
Operation During Sleep
As the reference clock module relies on the system
clock as its source, and the system clock is disabled in
Sleep, the module does not function in Sleep, even if
an external clock source or the Timer1 clock source is
configured as the system clock. The module outputs
will remain in their current state until the device exits
Sleep.
Note 1: If the base clock rate is selected without
a divider, the output clock will always
have a duty cycle equal to that of the
source clock, unless a 0% duty cycle is
selected. If the clock divider is set to base
clock/2, then 25% and 75% duty cycle
accuracy will be dependent upon the
source clock.
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