参数资料
型号: KSZ8995FQI
厂商: Micrel Inc
文件页数: 42/89页
文件大小: 0K
描述: IC SWITCH 10/100 5PORT 128-PQFP
标准包装: 66
系列: *
产品目录页面: 1081 (CN2011-ZH PDF)
配用: 576-3872-ND - BOARD EVALUATION FOR KSZ8995FQ
其它名称: 576-3300
Micrel, Inc.
KS8995MA/FQ
October 2011
47
M9999-102611-3.0
Global Registers
Address
Name
Description
Mode
Default
Register 0 (0x00): Chip ID0
7
0
Family ID
Chip Family.
RO
0x95
Address
Name
Description
Mode
Default
Register 1 (0x01): Chip ID1 / Start Switch
7
4
Chip ID
0x0 is assigned to M series. (95MA)
RO
0x0
3
1
Revision ID
RO
Based on real
chip revision.
0x02=B2,
0x03=B3,
0x04=B4,
0x05=B5, etc.
0
Start Switch
1, start the chip when external pins (PS1, PS0) = (1,0) or (0,1). Note:
in (PS1,PS0) = (0,0) mode, the chip will start automatically, after trying
to read the external EEPROM. If EEPROM does not exist, the chip will
use default values for all internal registers. If EEPROM is present, the
contents in the EEPROM will be checked.
The switch will check: (1) Register 0 = 0x95, (2) Register 1 [7:4] = 0x0.
If this check is OK, the contents in the EEPROM will override chip
register default values =0, chip will not start when external pins (PS1,
PS0) = (1,0) or (0,1).
Note: (PS1, PS0) = (1,1) for Factory test only.
RW
0x0
Address
Name
Description
Mode
Default
Register 2 (0x02): Global Control 0
7
Reserved
Reserved.
R/W
0x0
6
4
802.1p Base Priority
Used to classify priority for incoming 802.1q packets
“User priority” is compared against this value
⊕ : classified as high
priority.
< : classified as low priority.
R/W
0x4
3
Enable PHY MII
1, enable PHY MII-P5 interface.
Note: if not enabled, the switch will tri-state all outputs.
R/W
Pin LED5-1 strap
option.
Pull-down (0):
isolate. Pull-up
(1): Enable.
Note: LED[5][1]
has internal pull-
up.
2
Buffer Share Mode
1, buffer pool is shared by all ports. A port can use more buffer when
other ports are not busy.
0, a port is only allowed to use 1/5 of the buffer pool.
R/W
0x1
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