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参数资料
| 型号： | L64013A1 |
| 厂商： | LSI CORP |
| 元件分类： | 消费家电 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP100 |
| 封装： | PLASTIC, QFP-100 |
| 文件页数： | 15/16页 |
| 文件大小： | 273K |
| 代理商： | L64013A1 |
8
L64013 VIP Bridge
READ_N
Read
Output
The L64013 asserts READ_N LOW when it is performing
a bus read cycle. WRITE_N is HIGH during a read cycle.
When both CS_N and READ_N are LOW, the L64013 is
reading from the L64020’s internal registers.
WAIT_N
Device Wait
Input
The L64020 drives this active-LOW signal HIGH to
indicate to the L64013 that the current transaction can be
completed.
WRITE_N
Write
Output
Assertion of WRITE_N LOW indicates that the L64013 is
performing a write bus cycle. READ_N must be HIGH
during a write cycle. When both CS_N and WRITE_N are
LOW, the L64013 is writing to the L64020’s internal
registers.
L64020 Video Display Interface
DVDCLK_O
DVD Clock Output
Output
DVDCLK_O is the 27-MHz system clock for the L64020.
HS
Horizontal Sync Pulse
Output
HS resets the horizontal counters in the L64020. The
horizontal sync signal is synchronous with DVDCLK_O.
PDATA[7:0]
Pixel Data Output Bus
Input
The data on the PDATA[7:0] bus is the pixel data of the
reconstructed picture from the L64020.
VS
Vertical Sync Pulse
Output
The VS signal is a conventional vertical sync output. The
pulse width, frequency, and polarity are programmable.
Audio Clock Interface
SCLK
Serial Data Clock
Output
This clock operates at the same frequency as VIPCLK. It
is active only when the data in registers 0x292 and 0x293
is being written to the audio clock generator.
SDATA
Serial Data Output
Output
SDATA is the serial data output from registers 0x292 and
0x293.
L64013VIP Page 8 Friday, May 29, 1998 8:29 AM
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