参数资料
型号: L64020XBC
厂商: LSI CORP
元件分类: 消费家电
英文描述: SPECIALTY CONSUMER CIRCUIT, PQFP176
封装: PLASTIC, TQFP-176
文件页数: 7/32页
文件大小: 370K
代理商: L64020XBC
L64020 Single Chip DVD Decoder
15
DCK
Channel Clock
Input
The DCK is a free-running clock from the external
channel device. It must have a period
≥ 3x that of
SYSCLK (27 MHz). DCK, together with the AVALIDn and
VVALIDn signals, is used to write data synchronously to
the L64020 channel input.
Memory Interface
SCSn
SDRAM Chip Select
Output
The host asserts this signal to select the low address
SDRAM chip, the rst 2 Mbytes of memory. The
recommended SDRAM size for the L64020 is
2048 x 512 x 16 bits.
SCS1n
Second SDRAM Chip Select
Output
The host asserts this signal to select the high address
SDRAM chip in systems that have more than
2 Mbytes of memory. The high address SDRAM chip
must have the same page size as the low address
SDRAM chip but does not have to have the same number
of pages.
SDQM
SDRAM Control Pin
Output
SDQM is an active HIGH output signal for the SDRAM
data control mask.
SBA[11:0]
SDRAM Address Bus
Output
The row/column multiplexed address bus for SDRAM
memory. The L64020’s microcontroller and the host,
address SDRAM as if it were RAM. The Memory
Interface converts these addresses to SDRAM format.
SCASn
SDRAM Column Address Select
Output
The Memory Interface asserts this signal when the
SDRAM column address is on SBA[11:0].
SRASn
SDRAM Row Address Select
Output
The Memory Interface asserts this signal when the
SDRAM row address is on SBA[11:0].
SBD[15:0]
SDRAM Data Bus
Bidirectional
This 16-bit bidirectional data bus is directly connected to
1 M x 16 SDRAM(s) for buffering channel data and
reconstructed pictures.
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