参数资料
型号: L6564DTR
厂商: STMICROELECTRONICS
元件分类: 稳压器
英文描述: SWITCHING CONTROLLER, PDSO10
封装: ROHS COMPLIANT, SSOP-10
文件页数: 15/34页
文件大小: 809K
代理商: L6564DTR
Application information
L6564
22/34
Doc ID 16202 Rev 1
Figure 35.
Voltage feedforward: squarer-divider (1/V2) block diagram and transfer characteristic
In this way a change of the line voltage will cause an inversely proportional change of the
half sine amplitude at the output of the multiplier (if the line voltage doubles the amplitude of
the multiplier output will be halved and vice versa) so that the current reference is adapted to
the new operating conditions with (ideally) no need for invoking the slow dynamics of the
error amplifier. Additionally, the loop gain will be constant throughout the input voltage
range, which improves significantly dynamic behavior at low line and simplifies loop design.
Actually, deriving a voltage proportional to the RMS line voltage implies a form of integration,
which has its own time constant. If it is too small the voltage generated will be affected by a
considerable amount of ripple at twice the mains frequency that will cause distortion of the
current reference (resulting in high THD and poor PF); if it is too large there will be a
considerable delay in setting the right amount of feedforward, resulting in excessive
overshoot and undershoot of the pre-regulator's output voltage in response to large line
voltage changes. Clearly a trade-off was required.
The L6564 realizes a NEW voltage feed forward that, with a technique that makes use of
just two external parts, strongly minimizes this time constant trade-off issue whichever
voltage change occurs on the mains, both surges and drops. A capacitor CFF and a resistor
RFF, both connected from the pin VFF (#5) to ground, complete an internal peak-holding
circuit that provides a DC voltage equal to the peak of the rectified sine wave applied on pin
MULT (#3). In this way, in case of sudden line voltage rise, CFF will be rapidly charged
through the low impedance of the internal diode; in case of line voltage drop, an internal
“mains drop” detector enables a low impedance switch which suddenly discharges CFF
avoiding long settling time before reaching the new voltage level. Consequently, an
acceptably low steady-state ripple and low current distortion can be achieved without any
considerable undershoot or overshoot on the pre-regulator's output, like in systems with no
feedforward compensation.
The twice-mains-frequency (2fL) ripple appearing across CFF is triangular with a peak-to-
peak amplitude that, with good approximation, is given by:
FF
L
MULTpk
FF
C
R
f
4
1
V
2
V
+
=
Δ
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