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参数资料
| 型号： | L99PD08TR |
| 厂商： | STMICROELECTRONICS |
| 元件分类： | 电源管理 |
| 英文描述： | POWER SUPPLY MANAGEMENT CKT, PQFP32 |
| 封装： | ROHS COMPLIANT, LQFP-32 |
| 文件页数： | 24/41页 |
| 文件大小： | 750K |
| 代理商： | L99PD08TR |
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SPI
L99PD08
30/41
Doc ID 15872 Rev 3
Note:
If a channel is in ON-state (ON_OFF reg = ‘1’), the corresponding DEV_TYPE register is
write protected.
1
0
max time for serving the CSN set to 200ms
1
max time for serving the CSN set to 400ms
Table 26.
ON_OFF register, hex01 (RW-Type)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
CH7
CH6
CH5
CH4
CH3
CH2
CH1
CH0
CHx
0 Ox channel is switched off (default)
1 Ox channel is switched on
CHx
Output Ox
Table 27.
DEV_TYPE register, hex02 (RW-Type)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
CH7
CH6
CH5
CH4
CH3
CH2
CH1
CH0
CHx 0
Digital device is connected to device output (default)
1
Analog device is connected to device output
Table 28.
PWM_EN register, hex03 (RW-Type)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
CH7
CH6
CH5
CH4
CH3
CH2
CH1
CH0
CHx 0
If OUTx in ON_OFF register is 1, OUTx is switched in steady state mode (default)
1
If OUTx in ON_OFF register is 1, OUTx is switched in PWM mode
CHx Enables PWM mode on output Ox
Table 29.
CLK_SEL register, hex04 (RW-Type)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
CH7
CH6
CH5
CH4
CH3
CH2
CH1
CH0
CHx 0
The external clock source signal CLK_IN0 is selected for internal generation of
PWM signal for OUTx channel. The PWM period is the received clock signal
divided by 256 (default).
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