
LB11695M
No.7948-15/17
6. Control Methods
The output duty can be controlled by either of the following methods.
Using the voltage at the VCTL pin
Refer to the section entitled "Electrical Characteristics" for legitimate control voltages. Set the PWMIN pin to the
low level when controlling the output duty using the VCTL pin.
The IC is designed so that the 100% output duty cannot be achieved with the input through the VCTL pin in
consideration of possible application during bootstrap (the output duty is limited by the maximum output duty
specified in "Electrical Characteristics"). Consequently the motor speed must be controlled while adjusting the
output duty within the range of 0 to 80%.
Pulse Control Using the PWMIN Pin
A pulse signal can be input to the PWMIN pin, and the output can be
controlled based on the duty of that signal. Note that the output is on when a
low level is input to the PWMIN pin, and off when a high level is input.
When the PWMIN pin is open, it goes to the high level and the output is
turned off. If inverted input logic is required, this can be implemented with
an external transistor (npn).
When controlling motor operation using the PWMIN pin, the VCTL pin
must be connected to the VREG pin and a 2k
resistor must be inserted
between the TOC pin and ground. The use of this IC while controlling the
drive mode using the PWMIN pin during bootstrap is not taken into consideration.
7. Hall Input Signals
A signal input with an amplitude in excess of the hysteresis (50mV maximum) is required for the Hall inputs.
Considering the possibility of noise and phase displacement, an amplitude of 120mV or higher is desirable.
If disruptions to the output waveforms (during phase switching) or to the HP output (Hall signal output) occur due to
noise, this must be prevented by inserting capacitors between the inputs. The constraint protection circuit uses the
Hall inputs to identify the motor constraint state. Although the circuit is designed to tolerate a certain amount of noise,
care is required when using the constraint protection circuit.
If all three phases of the Hall input signal system go to the same input state, the outputs are all set to the off state (the
UL, VL, WL, UH, VH, and WH outputs all turn off).
If the outputs from a Hall IC are used, fixing one side of the inputs (either the + or - side) at a voltage within the
common-mode input voltage range allows the other input side to be used as an input over the 0 V to VCC1 range.
8. Undervoltage Protection Circuit
The undervoltage protection circuit turns one side of the outputs (UH, VH, and WH) off when the LVS pin voltage
falls below the minimum operation voltage (see the Electrical Characteristics). To prevent this circuit from repeatedly
turning the outputs on and off in the vicinity of the protection operating voltage, this circuit is designed with
hysteresis. Thus the output detected will not recover until the operating voltage rises by 0.5V (typical) with respect to
the operating voltage.
The protection operating voltage detection level is set up for the 5V system. The
detected voltage level can be increased by shifting the voltage by inserting a
zener diode in series with the LVS pin. The LVS sink current during detection
is about 65A. To increase the diode current to stabilize the zener diode voltage
rise, insert a resistor between the LVS pin and ground.
When the protection circuit is not to be used, do not keep the LVS pin open
(output is off when put in the open state); instead, a voltage of the level that will
not activate the circuit to the LVS pin.
To the
PWMIN pin
Pulse input
To detection
power supply
To LVS pin