参数资料
型号: LB11822
元件分类: 运动控制电子
英文描述: BRUSHLESS DC MOTOR CONTROLLER, 3.1 A, DFM28
封装: DIP-28
文件页数: 11/11页
文件大小: 144K
代理商: LB11822
No. 7105-9/11
LB11822
Overview of the LB11822
1. Speed control circuit
This IC performs speed control by using both the speed discriminator circuit and PLL circuit. The speed control circuit
outputs the error signal once for every two cycles of FG (one FG cycle counted). The PLL circuit outputs the phase
error signal once for each cycle of FG.
As the FG servo frequency is calculated as follows, the motor speed is set with the number of FG pulses and clock
frequency.
fFG(servo) = fCLK/512
fCLK: Clock frequency
This IC achieves variable speed control with ease when combined with LB11825M.
2. Output drive circuit
This IC employs a direct PWM drive method to minimize the power loss at output. The output Tr is always saturated
at ON, and the motor drive force is adjusted through change of the duty at which the output is turned ON. Since the
output PWM switching is made with the lower-side output Tr, it is necessary to connect the schottky diode between
OUT and VCC (because the through current flows at an instant when the lower-side Tr is turned ON if the diode with a
short reverse recovery time is not used). The diode between OUT and GND is incorporated. When the large output
current presents problem (waveform disturbance at kickback on the lower side), connect a commutating diode or
schottky diode externally.
3. Current limiting circuit
The current limiting circuit performs limiting with the current determined from I = VRF/Rf (VRF = 0.5 Vtyp, Rf:
current detector resistance) (that is, this circuit limits the peak current).
Limiting operation includes decrease in the output on-duty to suppress the current.
Pin No.
Pin
Function
Equivalent circuit
Continued from preceding page.
GND pin (Other than the output)
20
GND1
2 k
27
VREG
22
k
300
300
22
24
26
21
23
25
VREG
Hall amplifier input.
IN+ > IN– is the input high state, and the reverse is the input low
state.
It is recommended that the Hall signal has an amplitude of 100m
Vp-p (differential) or more.
Connect a capacitor between the IN+ and IN– inputs if there is
noise in the Hall sensor signals.
22
21
24
23
26
25
IN1+
IN1–
IN2+
IN2–
IN3+
IN3–
Forward/reverse control pin
Low: 0 V to 1.5 V
High: 3.5 V to VREG
H level when open
Hysteresis width about 0.5 V
27
F/R
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